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- #pragma once
- #ifdef __GNUC__
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wunused-parameter"
- #endif
- #ifndef LLVM_CODEGEN_TARGETLOWERING_H
- #define LLVM_CODEGEN_TARGETLOWERING_H
- #include "llvm/ADT/APInt.h"
- #include "llvm/ADT/ArrayRef.h"
- #include "llvm/ADT/DenseMap.h"
- #include "llvm/ADT/SmallVector.h"
- #include "llvm/ADT/StringRef.h"
- #include "llvm/CodeGen/ComplexDeinterleavingPass.h"
- #include "llvm/CodeGen/DAGCombine.h"
- #include "llvm/CodeGen/ISDOpcodes.h"
- #include "llvm/CodeGen/LowLevelType.h"
- #include "llvm/CodeGen/RuntimeLibcalls.h"
- #include "llvm/CodeGen/SelectionDAG.h"
- #include "llvm/CodeGen/SelectionDAGNodes.h"
- #include "llvm/CodeGen/TargetCallingConv.h"
- #include "llvm/CodeGen/ValueTypes.h"
- #include "llvm/IR/Attributes.h"
- #include "llvm/IR/CallingConv.h"
- #include "llvm/IR/DataLayout.h"
- #include "llvm/IR/DerivedTypes.h"
- #include "llvm/IR/Function.h"
- #include "llvm/IR/InlineAsm.h"
- #include "llvm/IR/Instruction.h"
- #include "llvm/IR/Instructions.h"
- #include "llvm/IR/Type.h"
- #include "llvm/Support/Alignment.h"
- #include "llvm/Support/AtomicOrdering.h"
- #include "llvm/Support/Casting.h"
- #include "llvm/Support/ErrorHandling.h"
- #include "llvm/Support/MachineValueType.h"
- #include <algorithm>
- #include <cassert>
- #include <climits>
- #include <cstdint>
- #include <iterator>
- #include <map>
- #include <string>
- #include <utility>
- #include <vector>
- namespace llvm {
- class AssumptionCache;
- class CCState;
- class CCValAssign;
- class Constant;
- class FastISel;
- class FunctionLoweringInfo;
- class GlobalValue;
- class Loop;
- class GISelKnownBits;
- class IntrinsicInst;
- class IRBuilderBase;
- struct KnownBits;
- class LegacyDivergenceAnalysis;
- class LLVMContext;
- class MachineBasicBlock;
- class MachineFunction;
- class MachineInstr;
- class MachineJumpTableInfo;
- class MachineLoop;
- class MachineRegisterInfo;
- class MCContext;
- class MCExpr;
- class Module;
- class ProfileSummaryInfo;
- class TargetLibraryInfo;
- class TargetMachine;
- class TargetRegisterClass;
- class TargetRegisterInfo;
- class TargetTransformInfo;
- class Value;
- namespace Sched {
- enum Preference {
- None,
- Source,
- RegPressure,
- Hybrid,
- ILP,
- VLIW,
- Fast,
- Linearize
- };
- }
- struct MemOp {
- private:
-
- uint64_t Size;
- bool DstAlignCanChange;
-
- Align DstAlign;
- bool AllowOverlap;
-
- bool IsMemset;
- bool ZeroMemset;
-
- bool MemcpyStrSrc;
-
- Align SrcAlign;
-
- public:
- static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign,
- Align SrcAlign, bool IsVolatile,
- bool MemcpyStrSrc = false) {
- MemOp Op;
- Op.Size = Size;
- Op.DstAlignCanChange = DstAlignCanChange;
- Op.DstAlign = DstAlign;
- Op.AllowOverlap = !IsVolatile;
- Op.IsMemset = false;
- Op.ZeroMemset = false;
- Op.MemcpyStrSrc = MemcpyStrSrc;
- Op.SrcAlign = SrcAlign;
- return Op;
- }
- static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign,
- bool IsZeroMemset, bool IsVolatile) {
- MemOp Op;
- Op.Size = Size;
- Op.DstAlignCanChange = DstAlignCanChange;
- Op.DstAlign = DstAlign;
- Op.AllowOverlap = !IsVolatile;
- Op.IsMemset = true;
- Op.ZeroMemset = IsZeroMemset;
- Op.MemcpyStrSrc = false;
- return Op;
- }
- uint64_t size() const { return Size; }
- Align getDstAlign() const {
- assert(!DstAlignCanChange);
- return DstAlign;
- }
- bool isFixedDstAlign() const { return !DstAlignCanChange; }
- bool allowOverlap() const { return AllowOverlap; }
- bool isMemset() const { return IsMemset; }
- bool isMemcpy() const { return !IsMemset; }
- bool isMemcpyWithFixedDstAlign() const {
- return isMemcpy() && !DstAlignCanChange;
- }
- bool isZeroMemset() const { return isMemset() && ZeroMemset; }
- bool isMemcpyStrSrc() const {
- assert(isMemcpy() && "Must be a memcpy");
- return MemcpyStrSrc;
- }
- Align getSrcAlign() const {
- assert(isMemcpy() && "Must be a memcpy");
- return SrcAlign;
- }
- bool isSrcAligned(Align AlignCheck) const {
- return isMemset() || llvm::isAligned(AlignCheck, SrcAlign.value());
- }
- bool isDstAligned(Align AlignCheck) const {
- return DstAlignCanChange || llvm::isAligned(AlignCheck, DstAlign.value());
- }
- bool isAligned(Align AlignCheck) const {
- return isSrcAligned(AlignCheck) && isDstAligned(AlignCheck);
- }
- };
- class TargetLoweringBase {
- public:
-
-
- enum LegalizeAction : uint8_t {
- Legal,
- Promote,
- Expand,
- LibCall,
- Custom
- };
-
-
- enum LegalizeTypeAction : uint8_t {
- TypeLegal,
- TypePromoteInteger,
- TypeExpandInteger,
- TypeSoftenFloat,
- TypeExpandFloat,
- TypeScalarizeVector,
- TypeSplitVector,
- TypeWidenVector,
- TypePromoteFloat,
- TypeSoftPromoteHalf,
- TypeScalarizeScalableVector,
-
-
-
-
-
-
- };
-
-
- using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
-
- enum BooleanContent {
- UndefinedBooleanContent,
- ZeroOrOneBooleanContent,
- ZeroOrNegativeOneBooleanContent
- };
-
- enum SelectSupportKind {
- ScalarValSelect,
- ScalarCondVectorVal,
-
- VectorMaskSelect
-
- };
-
-
-
-
- enum class AtomicExpansionKind {
- None,
- CastToInteger,
-
- LLSC,
-
- LLOnly,
-
- CmpXChg,
- MaskedIntrinsic,
- BitTestIntrinsic,
-
- CmpArithIntrinsic,
-
- Expand,
-
-
- NotAtomic
- };
-
- enum class MulExpansionKind {
- Always,
- OnlyLegalOrCustom,
-
- };
-
- enum class NegatibleCost {
- Cheaper = 0,
- Neutral = 1,
- Expensive = 2
- };
- class ArgListEntry {
- public:
- Value *Val = nullptr;
- SDValue Node = SDValue();
- Type *Ty = nullptr;
- bool IsSExt : 1;
- bool IsZExt : 1;
- bool IsInReg : 1;
- bool IsSRet : 1;
- bool IsNest : 1;
- bool IsByVal : 1;
- bool IsByRef : 1;
- bool IsInAlloca : 1;
- bool IsPreallocated : 1;
- bool IsReturned : 1;
- bool IsSwiftSelf : 1;
- bool IsSwiftAsync : 1;
- bool IsSwiftError : 1;
- bool IsCFGuardTarget : 1;
- MaybeAlign Alignment = std::nullopt;
- Type *IndirectType = nullptr;
- ArgListEntry()
- : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
- IsNest(false), IsByVal(false), IsByRef(false), IsInAlloca(false),
- IsPreallocated(false), IsReturned(false), IsSwiftSelf(false),
- IsSwiftAsync(false), IsSwiftError(false), IsCFGuardTarget(false) {}
- void setAttributes(const CallBase *Call, unsigned ArgIdx);
- };
- using ArgListTy = std::vector<ArgListEntry>;
- virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
- ArgListTy &Args) const {};
- static ISD::NodeType getExtendForContent(BooleanContent Content) {
- switch (Content) {
- case UndefinedBooleanContent:
-
- return ISD::ANY_EXTEND;
- case ZeroOrOneBooleanContent:
-
- return ISD::ZERO_EXTEND;
- case ZeroOrNegativeOneBooleanContent:
-
- return ISD::SIGN_EXTEND;
- }
- llvm_unreachable("Invalid content kind");
- }
- explicit TargetLoweringBase(const TargetMachine &TM);
- TargetLoweringBase(const TargetLoweringBase &) = delete;
- TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
- virtual ~TargetLoweringBase() = default;
-
- bool isStrictFPEnabled() const {
- return IsStrictFPEnabled;
- }
- protected:
-
- void initActions();
- public:
- const TargetMachine &getTargetMachine() const { return TM; }
- virtual bool useSoftFloat() const { return false; }
-
-
-
- virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
- return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
- }
-
-
-
- virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
- return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
- }
-
-
- MVT getFrameIndexTy(const DataLayout &DL) const {
- return getPointerTy(DL, DL.getAllocaAddrSpace());
- }
-
-
- MVT getProgramPointerTy(const DataLayout &DL) const {
- return getPointerTy(DL, DL.getProgramAddressSpace());
- }
-
-
- virtual MVT getFenceOperandTy(const DataLayout &DL) const {
- return getPointerTy(DL);
- }
-
-
-
- virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
-
-
-
-
-
-
-
- EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
- bool LegalTypes = true) const;
-
-
- LLVM_READONLY
- virtual LLT getPreferredShiftAmountTy(LLT ShiftValueTy) const {
- return ShiftValueTy;
- }
-
-
-
- virtual MVT getVectorIdxTy(const DataLayout &DL) const {
- return getPointerTy(DL);
- }
-
-
-
-
- virtual MVT getVPExplicitVectorLengthTy() const { return MVT::i32; }
-
-
-
- virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const {
- return MachineMemOperand::MONone;
- }
- MachineMemOperand::Flags
- getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL,
- AssumptionCache *AC = nullptr,
- const TargetLibraryInfo *LibInfo = nullptr) const;
- MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI,
- const DataLayout &DL) const;
- MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI,
- const DataLayout &DL) const;
- virtual bool isSelectSupported(SelectSupportKind ) const {
- return true;
- }
-
-
- virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const {
- return true;
- }
-
-
-
-
- virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
- return true;
- }
-
- bool hasMultipleConditionRegisters() const {
- return HasMultipleConditionRegisters;
- }
-
- bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
-
- virtual TargetLoweringBase::LegalizeTypeAction
- getPreferredVectorAction(MVT VT) const {
-
- if (VT.getVectorElementCount().isScalar())
- return TypeScalarizeVector;
-
- if (!VT.isPow2VectorType())
- return TypeWidenVector;
-
- return TypePromoteInteger;
- }
-
-
-
-
- virtual bool softPromoteHalfType() const { return false; }
-
-
-
-
-
-
-
-
-
- virtual bool
- shouldExpandBuildVectorWithShuffles(EVT ,
- unsigned DefinedValues) const {
- return DefinedValues < 3;
- }
-
-
-
-
- virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
-
- virtual bool hasStandaloneRem(EVT VT) const {
- return true;
- }
-
- virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
-
- return false;
- }
-
- enum ReciprocalEstimate : int {
- Unspecified = -1,
- Disabled = 0,
- Enabled = 1
- };
-
-
-
-
- int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
-
-
-
-
- int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
-
-
-
-
- int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
-
-
-
-
- int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
-
- bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
-
-
- const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
- return BypassSlowDivWidths;
- }
-
- virtual bool isVScaleKnownToBeAPowerOfTwo() const { return false; }
-
-
- bool isJumpExpensive() const { return JumpIsExpensive; }
-
-
- bool isPredictableSelectExpensive() const {
- return PredictableSelectIsExpensive;
- }
- virtual bool fallBackToDAGISel(const Instruction &Inst) const {
- return false;
- }
-
-
-
-
-
-
- virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
- const SelectionDAG &DAG,
- const MachineMemOperand &MMO) const;
-
-
- virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT,
- const SelectionDAG &DAG,
- const MachineMemOperand &MMO) const {
-
- return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO);
- }
-
-
-
- virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
- unsigned NumElem,
- unsigned AddrSpace) const {
- return false;
- }
-
-
-
- virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
- return true;
- }
-
- virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
- const MachineFunction &MF) const {
- return true;
- }
-
- virtual bool isCheapToSpeculateCttz(Type *Ty) const {
- return false;
- }
-
- virtual bool isCheapToSpeculateCtlz(Type *Ty) const {
- return false;
- }
-
- virtual bool isCtlzFast() const {
- return false;
- }
-
-
- virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const {
- return 1;
- }
-
-
- virtual bool isEqualityCmpFoldedWithSignedCmp() const { return true; }
-
-
- virtual bool preferZeroCompareBranch() const { return false; }
-
-
-
-
- virtual bool hasBitPreservingFPLogic(EVT VT) const {
- return false;
- }
-
-
- virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
- return false;
- }
-
-
-
-
-
-
-
-
-
-
- virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
- return false;
- }
-
-
-
-
-
- virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
- return false;
- }
-
-
-
-
- virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
- MVT VT = MVT::getIntegerVT(NumBits);
- return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
- }
-
-
-
-
-
-
-
-
-
-
-
-
- virtual bool hasAndNotCompare(SDValue Y) const {
- return false;
- }
-
-
-
- virtual bool hasAndNot(SDValue X) const {
-
-
- return hasAndNotCompare(X);
- }
-
-
-
-
- virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; }
-
-
-
-
-
- virtual bool shouldFoldMaskToVariableShiftPair(SDValue X) const {
-
- return false;
- }
-
-
-
-
- virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N,
- CombineLevel Level) const {
- return true;
- }
-
-
-
-
-
-
-
- virtual bool shouldTransformSignedTruncationCheck(EVT XVT,
- unsigned KeptBits) const {
-
- return false;
- }
-
-
-
-
-
-
-
- virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
- SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
- unsigned OldShiftOpcode, unsigned NewShiftOpcode,
- SelectionDAG &DAG) const {
- if (hasBitTest(X, Y)) {
-
-
-
-
- if (OldShiftOpcode == ISD::SHL && CC->isOne())
- return false;
-
- if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
- return true;
- }
-
-
-
-
- return !XC;
- }
-
-
-
-
-
- virtual bool preferIncOfAddToSubOfNot(EVT VT) const {
-
- return true;
- }
-
- virtual bool preferScalarizeSplat(unsigned Opc) const { return true; }
-
-
-
- bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
-
-
-
- virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
- unsigned &Cost) const {
- return false;
- }
-
-
- virtual bool shouldSplatInsEltVarIndex(EVT) const {
- return false;
- }
-
-
-
- virtual bool enableAggressiveFMAFusion(EVT VT) const { return false; }
-
-
-
- virtual bool enableAggressiveFMAFusion(LLT Ty) const { return false; }
-
- virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
- EVT VT) const;
-
-
-
- virtual
- MVT::SimpleValueType getCmpLibcallReturnType() const;
-
-
-
-
-
-
-
-
-
-
-
-
-
- BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
- if (isVec)
- return BooleanVectorContents;
- return isFloat ? BooleanFloatContents : BooleanContents;
- }
- BooleanContent getBooleanContents(EVT Type) const {
- return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
- }
-
-
-
-
-
- SDValue promoteTargetBoolean(SelectionDAG &DAG, SDValue Bool,
- EVT ValVT) const {
- SDLoc dl(Bool);
- EVT BoolVT =
- getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ValVT);
- ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(ValVT));
- return DAG.getNode(ExtendCode, dl, BoolVT, Bool);
- }
-
- Sched::Preference getSchedulingPreference() const {
- return SchedPreferenceInfo;
- }
-
-
-
- virtual Sched::Preference getSchedulingPreference(SDNode *) const {
- return Sched::None;
- }
-
-
- virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
- (void)isDivergent;
- const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
- assert(RC && "This value type is not natively supported!");
- return RC;
- }
-
-
-
- virtual bool requiresUniformRegister(MachineFunction &MF,
- const Value *) const {
- return false;
- }
-
-
-
-
-
-
-
- virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
- const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
- return RC;
- }
-
-
- virtual uint8_t getRepRegClassCostFor(MVT VT) const {
- return RepRegClassCostForVT[VT.SimpleTy];
- }
-
-
- enum class ShiftLegalizationStrategy {
- ExpandToParts,
- ExpandThroughStack,
- LowerToLibcall
- };
- virtual ShiftLegalizationStrategy
- preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
- unsigned ExpansionFactor) const {
- if (ExpansionFactor == 1)
- return ShiftLegalizationStrategy::ExpandToParts;
- return ShiftLegalizationStrategy::ExpandThroughStack;
- }
-
-
-
- bool isTypeLegal(EVT VT) const {
- assert(!VT.isSimple() ||
- (unsigned)VT.getSimpleVT().SimpleTy < std::size(RegClassForVT));
- return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
- }
- class ValueTypeActionImpl {
-
-
- LegalizeTypeAction ValueTypeActions[MVT::VALUETYPE_SIZE];
- public:
- ValueTypeActionImpl() {
- std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
- TypeLegal);
- }
- LegalizeTypeAction getTypeAction(MVT VT) const {
- return ValueTypeActions[VT.SimpleTy];
- }
- void setTypeAction(MVT VT, LegalizeTypeAction Action) {
- ValueTypeActions[VT.SimpleTy] = Action;
- }
- };
- const ValueTypeActionImpl &getValueTypeActions() const {
- return ValueTypeActions;
- }
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
-
-
-
-
- LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
- return getTypeConversion(Context, VT).first;
- }
- LegalizeTypeAction getTypeAction(MVT VT) const {
- return ValueTypeActions.getTypeAction(VT);
- }
-
-
-
-
-
-
- virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
- return getTypeConversion(Context, VT).second;
- }
-
-
-
-
- EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
- assert(!VT.isVector());
- while (true) {
- switch (getTypeAction(Context, VT)) {
- case TypeLegal:
- return VT;
- case TypeExpandInteger:
- VT = getTypeToTransformTo(Context, VT);
- break;
- default:
- llvm_unreachable("Type is not legal nor is it to be expanded!");
- }
- }
- }
-
-
-
-
-
-
-
-
- unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
- EVT &IntermediateVT,
- unsigned &NumIntermediates,
- MVT &RegisterVT) const;
-
-
-
- virtual unsigned getVectorTypeBreakdownForCallingConv(
- LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
- unsigned &NumIntermediates, MVT &RegisterVT) const {
- return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
- RegisterVT);
- }
- struct IntrinsicInfo {
- unsigned opc = 0;
- EVT memVT;
-
- PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
-
-
- std::optional<unsigned> fallbackAddressSpace;
- int offset = 0;
- uint64_t size = 0;
-
- MaybeAlign align = Align(1);
- MachineMemOperand::Flags flags = MachineMemOperand::MONone;
- IntrinsicInfo() = default;
- };
-
-
-
-
- virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
- MachineFunction &,
- unsigned ) const {
- return false;
- }
-
-
-
- virtual bool isFPImmLegal(const APFloat & , EVT ,
- bool ForCodeSize = false) const {
- return false;
- }
-
-
-
-
- virtual bool isShuffleMaskLegal(ArrayRef<int> , EVT ) const {
- return true;
- }
-
-
-
-
- virtual bool canOpTrap(unsigned Op, EVT VT) const;
-
-
-
- virtual bool isVectorClearMaskLegal(ArrayRef<int> ,
- EVT ) const {
- return false;
- }
-
- virtual LegalizeAction getCustomOperationAction(SDNode &Op) const {
- return Legal;
- }
-
-
-
- LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
- if (VT.isExtended()) return Expand;
-
-
- if (Op >= std::size(OpActions[0]))
- return Custom;
- return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
- }
-
-
-
- virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
- unsigned Scale) const {
- return false;
- }
-
-
-
-
- LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT,
- unsigned Scale) const {
- auto Action = getOperationAction(Op, VT);
- if (Action != Legal)
- return Action;
-
-
- bool Supported;
- switch (Op) {
- default:
- llvm_unreachable("Unexpected fixed point operation.");
- case ISD::SMULFIX:
- case ISD::SMULFIXSAT:
- case ISD::UMULFIX:
- case ISD::UMULFIXSAT:
- case ISD::SDIVFIX:
- case ISD::SDIVFIXSAT:
- case ISD::UDIVFIX:
- case ISD::UDIVFIXSAT:
- Supported = isSupportedFixedPointOperation(Op, VT, Scale);
- break;
- }
- return Supported ? Action : Expand;
- }
-
-
- LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const {
- unsigned EqOpc;
- switch (Op) {
- default: llvm_unreachable("Unexpected FP pseudo-opcode");
- #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
- case ISD::STRICT_##DAGN: EqOpc = ISD::DAGN; break;
- #define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
- case ISD::STRICT_##DAGN: EqOpc = ISD::SETCC; break;
- #include "llvm/IR/ConstrainedOps.def"
- }
- return getOperationAction(EqOpc, VT);
- }
-
-
-
-
- bool isOperationLegalOrCustom(unsigned Op, EVT VT,
- bool LegalOnly = false) const {
- if (LegalOnly)
- return isOperationLegal(Op, VT);
- return (VT == MVT::Other || isTypeLegal(VT)) &&
- (getOperationAction(Op, VT) == Legal ||
- getOperationAction(Op, VT) == Custom);
- }
-
-
-
-
- bool isOperationLegalOrPromote(unsigned Op, EVT VT,
- bool LegalOnly = false) const {
- if (LegalOnly)
- return isOperationLegal(Op, VT);
- return (VT == MVT::Other || isTypeLegal(VT)) &&
- (getOperationAction(Op, VT) == Legal ||
- getOperationAction(Op, VT) == Promote);
- }
-
-
-
-
- bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT,
- bool LegalOnly = false) const {
- if (LegalOnly)
- return isOperationLegal(Op, VT);
- return (VT == MVT::Other || isTypeLegal(VT)) &&
- (getOperationAction(Op, VT) == Legal ||
- getOperationAction(Op, VT) == Custom ||
- getOperationAction(Op, VT) == Promote);
- }
-
-
- bool isOperationCustom(unsigned Op, EVT VT) const {
- return getOperationAction(Op, VT) == Custom;
- }
-
- virtual bool areJTsAllowed(const Function *Fn) const {
- if (Fn->getFnAttribute("no-jump-tables").getValueAsBool())
- return false;
- return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
- isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
- }
-
- bool rangeFitsInWord(const APInt &Low, const APInt &High,
- const DataLayout &DL) const {
-
- uint64_t BW = DL.getIndexSizeInBits(0u);
- uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
- return Range <= BW;
- }
-
-
- virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
- uint64_t Range, ProfileSummaryInfo *PSI,
- BlockFrequencyInfo *BFI) const;
-
- virtual MVT getPreferredSwitchConditionType(LLVMContext &Context,
- EVT ConditionVT) const;
-
-
-
-
-
- bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
- const APInt &Low, const APInt &High,
- const DataLayout &DL) const {
-
-
-
-
-
-
- if (!rangeFitsInWord(Low, High, DL))
- return false;
-
-
-
-
-
- return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
- (NumDests == 3 && NumCmps >= 6);
- }
-
-
-
- bool isOperationExpand(unsigned Op, EVT VT) const {
- return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
- }
-
- bool isOperationLegal(unsigned Op, EVT VT) const {
- return (VT == MVT::Other || isTypeLegal(VT)) &&
- getOperationAction(Op, VT) == Legal;
- }
-
-
-
- LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
- EVT MemVT) const {
- if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
- unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
- unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
- assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::VALUETYPE_SIZE &&
- MemI < MVT::VALUETYPE_SIZE && "Table isn't big enough!");
- unsigned Shift = 4 * ExtType;
- return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
- }
-
- bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
- return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
- }
-
-
- bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
- return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
- getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
- }
-
-
-
- LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
- if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
- unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
- unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
- assert(ValI < MVT::VALUETYPE_SIZE && MemI < MVT::VALUETYPE_SIZE &&
- "Table isn't big enough!");
- return TruncStoreActions[ValI][MemI];
- }
-
-
- bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
- return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
- }
-
-
- bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
- return isTypeLegal(ValVT) &&
- (getTruncStoreAction(ValVT, MemVT) == Legal ||
- getTruncStoreAction(ValVT, MemVT) == Custom);
- }
- virtual bool canCombineTruncStore(EVT ValVT, EVT MemVT,
- bool LegalOnly) const {
- if (LegalOnly)
- return isTruncStoreLegal(ValVT, MemVT);
- return isTruncStoreLegalOrCustom(ValVT, MemVT);
- }
-
-
-
- LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
- return getIndexedModeAction(IdxMode, VT, IMAB_Load);
- }
-
- bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
- return VT.isSimple() &&
- (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
- getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
- }
-
-
-
- LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
- return getIndexedModeAction(IdxMode, VT, IMAB_Store);
- }
-
- bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
- return VT.isSimple() &&
- (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
- getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
- }
-
-
-
- LegalizeAction getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) const {
- return getIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad);
- }
-
- bool isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) const {
- return VT.isSimple() &&
- (getIndexedMaskedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
- getIndexedMaskedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
- }
-
-
-
- LegalizeAction getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) const {
- return getIndexedModeAction(IdxMode, VT, IMAB_MaskedStore);
- }
-
- bool isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const {
- return VT.isSimple() &&
- (getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
- getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
- }
-
-
- virtual bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const { return false; }
-
-
- virtual bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const {
- return false;
- }
-
-
-
- virtual bool isLegalScaleForGatherScatter(uint64_t Scale,
- uint64_t ElemSize) const {
-
-
- if (Scale != ElemSize && Scale != 1)
- return false;
- return true;
- }
-
-
-
- LegalizeAction
- getCondCodeAction(ISD::CondCode CC, MVT VT) const {
- assert((unsigned)CC < std::size(CondCodeActions) &&
- ((unsigned)VT.SimpleTy >> 3) < std::size(CondCodeActions[0]) &&
- "Table isn't big enough!");
-
- uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
- uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
- LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
- assert(Action != Promote && "Can't promote condition code!");
- return Action;
- }
-
- bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
- return getCondCodeAction(CC, VT) == Legal;
- }
-
-
- bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
- return getCondCodeAction(CC, VT) == Legal ||
- getCondCodeAction(CC, VT) == Custom;
- }
-
-
- MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
- assert(getOperationAction(Op, VT) == Promote &&
- "This operation isn't promoted!");
-
- std::map<std::pair<unsigned, MVT::SimpleValueType>,
- MVT::SimpleValueType>::const_iterator PTTI =
- PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
- if (PTTI != PromoteToType.end()) return PTTI->second;
- assert((VT.isInteger() || VT.isFloatingPoint()) &&
- "Cannot autopromote this type, add it with AddPromotedToType.");
- MVT NVT = VT;
- do {
- NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
- assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
- "Didn't find type to promote to!");
- } while (!isTypeLegal(NVT) ||
- getOperationAction(Op, NVT) == Promote);
- return NVT;
- }
- virtual EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty,
- bool AllowUnknown = false) const {
- return getValueType(DL, Ty, AllowUnknown);
- }
-
-
-
-
- EVT getValueType(const DataLayout &DL, Type *Ty,
- bool AllowUnknown = false) const {
-
- if (auto *PTy = dyn_cast<PointerType>(Ty))
- return getPointerTy(DL, PTy->getAddressSpace());
- if (auto *VTy = dyn_cast<VectorType>(Ty)) {
- Type *EltTy = VTy->getElementType();
-
- if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
- EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
- EltTy = PointerTy.getTypeForEVT(Ty->getContext());
- }
- return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false),
- VTy->getElementCount());
- }
- return EVT::getEVT(Ty, AllowUnknown);
- }
- EVT getMemValueType(const DataLayout &DL, Type *Ty,
- bool AllowUnknown = false) const {
-
- if (PointerType *PTy = dyn_cast<PointerType>(Ty))
- return getPointerMemTy(DL, PTy->getAddressSpace());
- else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
- Type *Elm = VTy->getElementType();
- if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
- EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
- Elm = PointerTy.getTypeForEVT(Ty->getContext());
- }
- return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
- VTy->getElementCount());
- }
- return getValueType(DL, Ty, AllowUnknown);
- }
-
- MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
- bool AllowUnknown = false) const {
- return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
- }
-
-
-
- virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
-
- MVT getRegisterType(MVT VT) const {
- assert((unsigned)VT.SimpleTy < std::size(RegisterTypeForVT));
- return RegisterTypeForVT[VT.SimpleTy];
- }
-
- MVT getRegisterType(LLVMContext &Context, EVT VT) const {
- if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT().SimpleTy <
- std::size(RegisterTypeForVT));
- return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
- }
- if (VT.isVector()) {
- EVT VT1;
- MVT RegisterVT;
- unsigned NumIntermediates;
- (void)getVectorTypeBreakdown(Context, VT, VT1,
- NumIntermediates, RegisterVT);
- return RegisterVT;
- }
- if (VT.isInteger()) {
- return getRegisterType(Context, getTypeToTransformTo(Context, VT));
- }
- llvm_unreachable("Unsupported extended type!");
- }
-
-
-
-
-
-
-
-
-
-
-
- virtual unsigned
- getNumRegisters(LLVMContext &Context, EVT VT,
- std::optional<MVT> RegisterVT = std::nullopt) const {
- if (VT.isSimple()) {
- assert((unsigned)VT.getSimpleVT().SimpleTy <
- std::size(NumRegistersForVT));
- return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
- }
- if (VT.isVector()) {
- EVT VT1;
- MVT VT2;
- unsigned NumIntermediates;
- return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
- }
- if (VT.isInteger()) {
- unsigned BitWidth = VT.getSizeInBits();
- unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
- return (BitWidth + RegWidth - 1) / RegWidth;
- }
- llvm_unreachable("Unsupported extended type!");
- }
-
-
-
- virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
- CallingConv::ID CC, EVT VT) const {
- return getRegisterType(Context, VT);
- }
-
-
-
- virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
- CallingConv::ID CC,
- EVT VT) const {
- return getNumRegisters(Context, VT);
- }
-
-
- virtual Align getABIAlignmentForCallingConv(Type *ArgTy,
- const DataLayout &DL) const {
- return DL.getABITypeAlign(ArgTy);
- }
-
-
-
- virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
-
-
- virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
- EVT NewVT) const {
-
-
- if (NewVT.isVector() && !Load->hasOneUse())
- return false;
- return true;
- }
-
-
-
- bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
- return DL.isBigEndian() || VT == MVT::ppcf128;
- }
-
-
- bool hasTargetDAGCombine(ISD::NodeType NT) const {
- assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
- return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
- }
- unsigned getGatherAllAliasesMaxDepth() const {
- return GatherAllAliasesMaxDepth;
- }
-
- virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
- return getPointerTy(DL).getSizeInBits();
- }
-
-
-
-
-
-
- unsigned getMaxStoresPerMemset(bool OptSize) const {
- return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
- }
-
-
-
-
-
-
- unsigned getMaxStoresPerMemcpy(bool OptSize) const {
- return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
- }
-
-
-
-
-
- virtual unsigned getMaxGluedStoresPerMemcpy() const {
- return MaxGluedStoresPerMemcpy;
- }
-
-
-
-
-
-
- unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
- return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
- }
-
-
-
-
-
-
- unsigned getMaxStoresPerMemmove(bool OptSize) const {
- return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
- }
-
-
-
-
-
-
-
-
-
-
- virtual bool allowsMisalignedMemoryAccesses(
- EVT, unsigned AddrSpace = 0, Align Alignment = Align(1),
- MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
- unsigned * = nullptr) const {
- return false;
- }
-
- virtual bool allowsMisalignedMemoryAccesses(
- LLT, unsigned AddrSpace = 0, Align Alignment = Align(1),
- MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
- unsigned * = nullptr) const {
- return false;
- }
-
-
-
-
- bool allowsMemoryAccessForAlignment(
- LLVMContext &Context, const DataLayout &DL, EVT VT,
- unsigned AddrSpace = 0, Align Alignment = Align(1),
- MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
- unsigned *Fast = nullptr) const;
-
-
-
-
- bool allowsMemoryAccessForAlignment(LLVMContext &Context,
- const DataLayout &DL, EVT VT,
- const MachineMemOperand &MMO,
- unsigned *Fast = nullptr) const;
-
-
-
-
- virtual bool
- allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
- unsigned AddrSpace = 0, Align Alignment = Align(1),
- MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
- unsigned *Fast = nullptr) const;
-
-
-
-
- bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
- const MachineMemOperand &MMO,
- unsigned *Fast = nullptr) const;
-
- bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, LLT Ty,
- const MachineMemOperand &MMO,
- unsigned *Fast = nullptr) const;
-
-
-
-
- virtual EVT
- getOptimalMemOpType(const MemOp &Op,
- const AttributeList & ) const {
- return MVT::Other;
- }
-
- virtual LLT
- getOptimalMemOpLLT(const MemOp &Op,
- const AttributeList & ) const {
- return LLT();
- }
-
-
-
-
-
-
-
- virtual bool isSafeMemOpType(MVT ) const { return true; }
-
- virtual unsigned getMinimumJumpTableEntries() const;
-
- unsigned getMinimumJumpTableDensity(bool OptForSize) const;
-
-
- unsigned getMaximumJumpTableSize() const;
- virtual bool isJumpTableRelative() const;
-
-
- Register getStackPointerRegisterToSaveRestore() const {
- return StackPointerRegisterToSaveRestore;
- }
-
-
- virtual Register
- getExceptionPointerRegister(const Constant *PersonalityFn) const {
- return Register();
- }
-
-
- virtual Register
- getExceptionSelectorRegister(const Constant *PersonalityFn) const {
- return Register();
- }
- virtual bool needsFixedCatchObjects() const {
- report_fatal_error("Funclet EH is not implemented for this target");
- }
-
- Align getMinStackArgumentAlignment() const {
- return MinStackArgumentAlignment;
- }
-
- Align getMinFunctionAlignment() const { return MinFunctionAlignment; }
-
- Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
-
- virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const;
-
-
- virtual unsigned
- getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const;
-
-
- virtual bool alignLoopsWithOptSize() const { return false; }
-
-
-
-
- virtual Value *getIRStackGuard(IRBuilderBase &IRB) const;
-
-
- virtual void insertSSPDeclarations(Module &M) const;
-
-
-
- virtual Value *getSDagStackGuard(const Module &M) const;
-
-
-
-
- virtual bool useStackGuardXorFP() const { return false; }
-
-
-
-
- virtual Function *getSSPStackGuardCheck(const Module &M) const;
-
- virtual bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
- LLT Ty2) const {
- return false;
- }
- protected:
- Value *getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
- bool UseTLS) const;
- public:
-
- virtual Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const;
-
-
- virtual bool hasStackProbeSymbol(const MachineFunction &MF) const { return false; }
- virtual bool hasInlineStackProbe(const MachineFunction &MF) const { return false; }
- virtual StringRef getStackProbeSymbolName(const MachineFunction &MF) const {
- return "";
- }
-
-
-
- virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const;
-
-
-
-
- virtual bool shouldAlignPointerArgs(CallInst * , unsigned & ,
- Align & ) const {
- return false;
- }
-
-
-
-
- int InstructionOpcodeToISD(unsigned Opcode) const;
-
-
-
-
-
-
-
-
- unsigned getMaxAtomicSizeInBitsSupported() const {
- return MaxAtomicSizeInBitsSupported;
- }
-
-
- unsigned getMaxDivRemBitWidthSupported() const {
- return MaxDivRemBitWidthSupported;
- }
-
-
- unsigned getMaxLargeFPConvertBitWidthSupported() const {
- return MaxLargeFPConvertBitWidthSupported;
- }
-
-
-
-
-
-
-
- unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
-
- bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
-
-
-
- virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
- return false;
- }
-
-
- virtual bool
- shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const {
- return false;
- }
-
-
-
-
- virtual Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy,
- Value *Addr, AtomicOrdering Ord) const {
- llvm_unreachable("Load linked unimplemented on this target");
- }
-
-
- virtual Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val,
- Value *Addr, AtomicOrdering Ord) const {
- llvm_unreachable("Store conditional unimplemented on this target");
- }
-
-
-
-
- virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder,
- AtomicRMWInst *AI,
- Value *AlignedAddr, Value *Incr,
- Value *Mask, Value *ShiftAmt,
- AtomicOrdering Ord) const {
- llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
- }
-
-
-
- virtual void emitExpandAtomicRMW(AtomicRMWInst *AI) const {
- llvm_unreachable(
- "Generic atomicrmw expansion unimplemented on this target");
- }
-
-
-
- virtual void emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const {
- llvm_unreachable(
- "Bit test atomicrmw expansion unimplemented on this target");
- }
-
-
-
- virtual void emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) const {
- llvm_unreachable(
- "Compare arith atomicrmw expansion unimplemented on this target");
- }
-
-
-
-
- virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
- IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
- Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
- llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
- }
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- virtual Instruction *emitLeadingFence(IRBuilderBase &Builder,
- Instruction *Inst,
- AtomicOrdering Ord) const;
- virtual Instruction *emitTrailingFence(IRBuilderBase &Builder,
- Instruction *Inst,
- AtomicOrdering Ord) const;
-
-
-
-
-
-
-
- virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const {}
-
- virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
- return IsSigned;
- }
-
- virtual bool shouldExtendTypeInLibCall(EVT Type) const {
- return true;
- }
-
-
- virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
- return AtomicExpansionKind::None;
- }
-
-
- virtual AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const {
- if (LI->getType()->isFloatingPointTy())
- return AtomicExpansionKind::CastToInteger;
- return AtomicExpansionKind::None;
- }
-
-
-
- virtual AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const {
- return AtomicExpansionKind::None;
- }
-
-
-
- virtual AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const {
- if (SI->getValueOperand()->getType()->isFloatingPointTy())
- return AtomicExpansionKind::CastToInteger;
- return AtomicExpansionKind::None;
- }
-
-
- virtual AtomicExpansionKind
- shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
- return AtomicExpansionKind::None;
- }
-
-
- virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
- return RMW->isFloatingPointOperation() ?
- AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
- }
-
-
- virtual AtomicExpansionKind
- shouldCastAtomicRMWIInIR(AtomicRMWInst *RMWI) const {
- if (RMWI->getOperation() == AtomicRMWInst::Xchg &&
- (RMWI->getValOperand()->getType()->isFloatingPointTy() ||
- RMWI->getValOperand()->getType()->isPointerTy()))
- return AtomicExpansionKind::CastToInteger;
- return AtomicExpansionKind::None;
- }
-
-
-
-
-
-
-
-
-
-
-
- virtual LoadInst *
- lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
- return nullptr;
- }
-
-
- virtual ISD::NodeType getExtendForAtomicOps() const {
- return ISD::ZERO_EXTEND;
- }
-
-
-
-
-
-
-
-
- virtual ISD::NodeType getExtendForAtomicCmpSwapArg() const {
- return ISD::ANY_EXTEND;
- }
-
-
-
-
-
-
- virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
- EVT VT) const {
-
-
- if (hasMultipleConditionRegisters())
- return false;
-
-
- LegalizeTypeAction Action = getTypeAction(Context, VT);
- return Action != TypeExpandInteger && Action != TypeExpandFloat &&
- Action != TypeSplitVector;
- }
- virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
-
-
-
- virtual bool convertSelectOfConstantsToMath(EVT VT) const {
- return false;
- }
-
-
-
-
-
- virtual bool decomposeMulByConstant(LLVMContext &Context,
- EVT VT, SDValue C) const {
- return false;
- }
-
-
-
-
-
-
-
-
-
- virtual bool isMulAddWithConstProfitable(SDValue AddNode,
- SDValue ConstNode) const {
- return true;
- }
-
-
-
-
-
- virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
- bool IsSigned) const {
- return false;
- }
-
-
-
-
-
- bool isBeneficialToExpandPowI(int Exponent, bool OptForSize) const {
- if (Exponent < 0)
- Exponent = -Exponent;
- return !OptForSize ||
- (llvm::popcount((unsigned int)Exponent) + Log2_32(Exponent) < 7);
- }
-
-
-
-
- protected:
-
-
- void setBooleanContents(BooleanContent Ty) {
- BooleanContents = Ty;
- BooleanFloatContents = Ty;
- }
-
-
- void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
- BooleanContents = IntTy;
- BooleanFloatContents = FloatTy;
- }
-
-
- void setBooleanVectorContents(BooleanContent Ty) {
- BooleanVectorContents = Ty;
- }
-
- void setSchedulingPreference(Sched::Preference Pref) {
- SchedPreferenceInfo = Pref;
- }
-
- void setMinimumJumpTableEntries(unsigned Val);
-
-
- void setMaximumJumpTableSize(unsigned);
-
-
- void setStackPointerRegisterToSaveRestore(Register R) {
- StackPointerRegisterToSaveRestore = R;
- }
-
-
-
-
-
- void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
- HasMultipleConditionRegisters = hasManyRegs;
- }
-
-
-
-
- void setHasExtractBitsInsn(bool hasExtractInsn = true) {
- HasExtractBitsInsn = hasExtractInsn;
- }
-
-
-
- void setJumpIsExpensive(bool isExpensive = true);
-
- void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
- BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
- }
-
-
-
- void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
- assert((unsigned)VT.SimpleTy < std::size(RegClassForVT));
- RegClassForVT[VT.SimpleTy] = RC;
- }
-
-
- virtual std::pair<const TargetRegisterClass *, uint8_t>
- findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
-
-
- void computeRegisterProperties(const TargetRegisterInfo *TRI);
-
-
-
- void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) {
- assert(Op < std::size(OpActions[0]) && "Table isn't big enough!");
- OpActions[(unsigned)VT.SimpleTy][Op] = Action;
- }
- void setOperationAction(ArrayRef<unsigned> Ops, MVT VT,
- LegalizeAction Action) {
- for (auto Op : Ops)
- setOperationAction(Op, VT, Action);
- }
- void setOperationAction(ArrayRef<unsigned> Ops, ArrayRef<MVT> VTs,
- LegalizeAction Action) {
- for (auto VT : VTs)
- setOperationAction(Ops, VT, Action);
- }
-
-
- void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
- LegalizeAction Action) {
- assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
- MemVT.isValid() && "Table isn't big enough!");
- assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
- unsigned Shift = 4 * ExtType;
- LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
- LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
- }
- void setLoadExtAction(ArrayRef<unsigned> ExtTypes, MVT ValVT, MVT MemVT,
- LegalizeAction Action) {
- for (auto ExtType : ExtTypes)
- setLoadExtAction(ExtType, ValVT, MemVT, Action);
- }
- void setLoadExtAction(ArrayRef<unsigned> ExtTypes, MVT ValVT,
- ArrayRef<MVT> MemVTs, LegalizeAction Action) {
- for (auto MemVT : MemVTs)
- setLoadExtAction(ExtTypes, ValVT, MemVT, Action);
- }
-
-
- void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action) {
- assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
- TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
- }
-
-
-
-
-
- void setIndexedLoadAction(ArrayRef<unsigned> IdxModes, MVT VT,
- LegalizeAction Action) {
- for (auto IdxMode : IdxModes)
- setIndexedModeAction(IdxMode, VT, IMAB_Load, Action);
- }
- void setIndexedLoadAction(ArrayRef<unsigned> IdxModes, ArrayRef<MVT> VTs,
- LegalizeAction Action) {
- for (auto VT : VTs)
- setIndexedLoadAction(IdxModes, VT, Action);
- }
-
-
-
-
-
- void setIndexedStoreAction(ArrayRef<unsigned> IdxModes, MVT VT,
- LegalizeAction Action) {
- for (auto IdxMode : IdxModes)
- setIndexedModeAction(IdxMode, VT, IMAB_Store, Action);
- }
- void setIndexedStoreAction(ArrayRef<unsigned> IdxModes, ArrayRef<MVT> VTs,
- LegalizeAction Action) {
- for (auto VT : VTs)
- setIndexedStoreAction(IdxModes, VT, Action);
- }
-
-
-
-
-
- void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT,
- LegalizeAction Action) {
- setIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad, Action);
- }
-
-
-
-
-
- void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT,
- LegalizeAction Action) {
- setIndexedModeAction(IdxMode, VT, IMAB_MaskedStore, Action);
- }
-
-
- void setCondCodeAction(ArrayRef<ISD::CondCode> CCs, MVT VT,
- LegalizeAction Action) {
- for (auto CC : CCs) {
- assert(VT.isValid() && (unsigned)CC < std::size(CondCodeActions) &&
- "Table isn't big enough!");
- assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
-
-
-
- uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
- CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
- CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
- }
- }
- void setCondCodeAction(ArrayRef<ISD::CondCode> CCs, ArrayRef<MVT> VTs,
- LegalizeAction Action) {
- for (auto VT : VTs)
- setCondCodeAction(CCs, VT, Action);
- }
-
-
-
-
- void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
- PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
- }
-
-
- void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
- setOperationAction(Opc, OrigVT, Promote);
- AddPromotedToType(Opc, OrigVT, DestVT);
- }
-
-
-
- void setTargetDAGCombine(ArrayRef<ISD::NodeType> NTs) {
- for (auto NT : NTs) {
- assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
- TargetDAGCombineArray[NT >> 3] |= 1 << (NT & 7);
- }
- }
-
- void setMinFunctionAlignment(Align Alignment) {
- MinFunctionAlignment = Alignment;
- }
-
-
- void setPrefFunctionAlignment(Align Alignment) {
- PrefFunctionAlignment = Alignment;
- }
-
-
-
- void setPrefLoopAlignment(Align Alignment) { PrefLoopAlignment = Alignment; }
- void setMaxBytesForAlignment(unsigned MaxBytes) {
- MaxBytesForAlignment = MaxBytes;
- }
-
- void setMinStackArgumentAlignment(Align Alignment) {
- MinStackArgumentAlignment = Alignment;
- }
-
-
-
-
- void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
- MaxAtomicSizeInBitsSupported = SizeInBits;
- }
-
-
- void setMaxDivRemBitWidthSupported(unsigned SizeInBits) {
- MaxDivRemBitWidthSupported = SizeInBits;
- }
-
-
- void setMaxLargeFPConvertBitWidthSupported(unsigned SizeInBits) {
- MaxLargeFPConvertBitWidthSupported = SizeInBits;
- }
-
- void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
- MinCmpXchgSizeInBits = SizeInBits;
- }
-
- void setSupportsUnalignedAtomics(bool UnalignedSupported) {
- SupportsUnalignedAtomics = UnalignedSupported;
- }
- public:
-
-
-
-
-
-
-
-
- virtual bool getAddrModeArguments(IntrinsicInst * ,
- SmallVectorImpl<Value*> &,
- Type *&) const {
- return false;
- }
-
-
-
-
-
-
-
- struct AddrMode {
- GlobalValue *BaseGV = nullptr;
- int64_t BaseOffs = 0;
- bool HasBaseReg = false;
- int64_t Scale = 0;
- AddrMode() = default;
- };
-
-
-
-
-
-
-
-
-
-
- virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
- Type *Ty, unsigned AddrSpace,
- Instruction *I = nullptr) const;
-
-
-
- virtual bool isLegalICmpImmediate(int64_t) const {
- return true;
- }
-
-
-
- virtual bool isLegalAddImmediate(int64_t) const {
- return true;
- }
-
-
- virtual bool isLegalStoreImmediate(int64_t Value) const {
-
-
- return Value == 0;
- }
-
-
-
-
-
- virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
- return false;
- }
-
-
-
-
-
- virtual Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const {
- return nullptr;
- }
-
-
-
- virtual bool shouldConvertPhiType(Type *From, Type *To) const {
- return (From->isIntegerTy() || From->isFloatingPointTy()) &&
- (To->isIntegerTy() || To->isFloatingPointTy());
- }
-
- virtual bool isCommutativeBinOp(unsigned Opcode) const {
-
- switch (Opcode) {
- case ISD::ADD:
- case ISD::SMIN:
- case ISD::SMAX:
- case ISD::UMIN:
- case ISD::UMAX:
- case ISD::MUL:
- case ISD::MULHU:
- case ISD::MULHS:
- case ISD::SMUL_LOHI:
- case ISD::UMUL_LOHI:
- case ISD::FADD:
- case ISD::FMUL:
- case ISD::AND:
- case ISD::OR:
- case ISD::XOR:
- case ISD::SADDO:
- case ISD::UADDO:
- case ISD::ADDC:
- case ISD::ADDE:
- case ISD::SADDSAT:
- case ISD::UADDSAT:
- case ISD::FMINNUM:
- case ISD::FMAXNUM:
- case ISD::FMINNUM_IEEE:
- case ISD::FMAXNUM_IEEE:
- case ISD::FMINIMUM:
- case ISD::FMAXIMUM:
- case ISD::AVGFLOORS:
- case ISD::AVGFLOORU:
- case ISD::AVGCEILS:
- case ISD::AVGCEILU:
- return true;
- default: return false;
- }
- }
-
- virtual bool isBinOp(unsigned Opcode) const {
-
- if (isCommutativeBinOp(Opcode))
- return true;
-
- switch (Opcode) {
- case ISD::SUB:
- case ISD::SHL:
- case ISD::SRL:
- case ISD::SRA:
- case ISD::ROTL:
- case ISD::ROTR:
- case ISD::SDIV:
- case ISD::UDIV:
- case ISD::SREM:
- case ISD::UREM:
- case ISD::SSUBSAT:
- case ISD::USUBSAT:
- case ISD::FSUB:
- case ISD::FDIV:
- case ISD::FREM:
- return true;
- default:
- return false;
- }
- }
-
-
-
-
- virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
- return false;
- }
-
-
-
-
-
- virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
- return false;
- }
- virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const { return false; }
- virtual bool isTruncateFree(LLT FromTy, LLT ToTy, const DataLayout &DL,
- LLVMContext &Ctx) const {
- return isTruncateFree(getApproximateEVTForLLT(FromTy, DL, Ctx),
- getApproximateEVTForLLT(ToTy, DL, Ctx));
- }
- virtual bool isProfitableToHoist(Instruction *I) const { return true; }
-
-
-
-
-
-
-
-
-
- bool isExtFree(const Instruction *I) const {
- switch (I->getOpcode()) {
- case Instruction::FPExt:
- if (isFPExtFree(EVT::getEVT(I->getType()),
- EVT::getEVT(I->getOperand(0)->getType())))
- return true;
- break;
- case Instruction::ZExt:
- if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
- return true;
- break;
- case Instruction::SExt:
- break;
- default:
- llvm_unreachable("Instruction is not an extension");
- }
- return isExtFreeImpl(I);
- }
-
-
-
-
-
-
- bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
- const DataLayout &DL) const {
- EVT VT = getValueType(DL, Ext->getType());
- EVT LoadVT = getValueType(DL, Load->getType());
-
-
- if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
- !isTruncateFree(Ext->getType(), Load->getType()))
- return false;
-
- unsigned LType;
- if (isa<ZExtInst>(Ext))
- LType = ISD::ZEXTLOAD;
- else {
- assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
- LType = ISD::SEXTLOAD;
- }
- return isLoadExtLegal(LType, VT, LoadVT);
- }
-
-
-
-
-
-
-
-
-
-
- virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
- return false;
- }
- virtual bool isZExtFree(EVT FromTy, EVT ToTy) const { return false; }
- virtual bool isZExtFree(LLT FromTy, LLT ToTy, const DataLayout &DL,
- LLVMContext &Ctx) const {
- return isZExtFree(getApproximateEVTForLLT(FromTy, DL, Ctx),
- getApproximateEVTForLLT(ToTy, DL, Ctx));
- }
-
-
- virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
- return false;
- }
-
-
- virtual bool signExtendConstant(const ConstantInt *C) const { return false; }
-
-
-
-
-
- virtual bool shouldSinkOperands(Instruction *I,
- SmallVectorImpl<Use *> &Ops) const {
- return false;
- }
-
-
- virtual bool optimizeExtendOrTruncateConversion(Instruction *I,
- Loop *L) const {
- return false;
- }
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- virtual bool hasPairedLoad(EVT ,
- Align & ) const {
- return false;
- }
-
- virtual bool hasVectorBlend() const { return false; }
-
-
- virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
-
-
-
-
-
-
-
- virtual bool lowerInterleavedLoad(LoadInst *LI,
- ArrayRef<ShuffleVectorInst *> Shuffles,
- ArrayRef<unsigned> Indices,
- unsigned Factor) const {
- return false;
- }
-
-
-
-
-
-
- virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
- unsigned Factor) const {
- return false;
- }
-
-
-
- virtual bool isZExtFree(SDValue Val, EVT VT2) const {
- return isZExtFree(Val.getValueType(), VT2);
- }
-
-
-
- virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
- assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
- "invalid fpext types");
- return false;
- }
-
-
-
- virtual bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode,
- LLT DestTy, LLT SrcTy) const {
- return false;
- }
-
-
-
- virtual bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
- EVT DestVT, EVT SrcVT) const {
- assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
- "invalid fpext types");
- return isFPExtFree(DestVT, SrcVT);
- }
-
-
- virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
-
-
- virtual bool isFNegFree(EVT VT) const {
- assert(VT.isFloatingPoint());
- return false;
- }
-
-
- virtual bool isFAbsFree(EVT VT) const {
- assert(VT.isFloatingPoint());
- return false;
- }
-
-
-
-
-
-
-
-
- virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
- EVT) const {
- return false;
- }
-
-
-
-
-
-
-
-
- virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
- LLT) const {
- return false;
- }
-
- virtual bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *) const {
- return false;
- }
-
-
-
-
- virtual bool isFMADLegal(const MachineInstr &MI, LLT Ty) const {
- assert((MI.getOpcode() == TargetOpcode::G_FADD ||
- MI.getOpcode() == TargetOpcode::G_FSUB ||
- MI.getOpcode() == TargetOpcode::G_FMUL) &&
- "unexpected node in FMAD forming combine");
- switch (Ty.getScalarSizeInBits()) {
- case 16:
- return isOperationLegal(TargetOpcode::G_FMAD, MVT::f16);
- case 32:
- return isOperationLegal(TargetOpcode::G_FMAD, MVT::f32);
- case 64:
- return isOperationLegal(TargetOpcode::G_FMAD, MVT::f64);
- default:
- break;
- }
- return false;
- }
-
-
-
- virtual bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const {
- assert((N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB ||
- N->getOpcode() == ISD::FMUL) &&
- "unexpected node in FMAD forming combine");
- return isOperationLegal(ISD::FMAD, N->getValueType(0));
- }
-
-
- virtual bool generateFMAsInMachineCombiner(EVT VT,
- CodeGenOpt::Level OptLevel) const {
- return false;
- }
-
-
-
- virtual bool isNarrowingProfitable(EVT , EVT ) const {
- return false;
- }
-
-
-
- virtual bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
- EVT VT) const {
- return false;
- }
-
-
-
-
-
- virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
- Type *Ty) const {
- return false;
- }
-
-
-
-
- virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
- unsigned Index) const {
- return false;
- }
-
-
- virtual bool shouldScalarizeBinop(SDValue VecOp) const {
- return false;
- }
-
-
-
-
- virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
- return false;
- }
-
-
-
-
- virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
- bool MathUsed) const {
-
-
- if (Opcode != ISD::UADDO)
- return false;
-
-
-
-
-
- if (VT.isVector())
- return false;
- return MathUsed && (VT.isSimple() || !isOperationExpand(Opcode, VT));
- }
-
-
- virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
- return false;
- }
-
-
-
- virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
-
-
- virtual bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const {
- return false;
- }
-
-
- virtual bool shouldKeepZExtForFP16Conv() const { return false; }
-
-
- virtual bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const {
- return isOperationLegalOrCustom(Op, VT);
- }
-
- virtual bool isComplexDeinterleavingSupported() const { return false; }
-
-
- virtual bool isComplexDeinterleavingOperationSupported(
- ComplexDeinterleavingOperation Operation, Type *Ty) const {
- return false;
- }
-
-
-
- virtual Value *createComplexDeinterleavingIR(
- Instruction *I, ComplexDeinterleavingOperation OperationType,
- ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
- Value *Accumulator = nullptr) const {
- return nullptr;
- }
-
-
-
-
- void setLibcallName(RTLIB::Libcall Call, const char *Name) {
- LibcallRoutineNames[Call] = Name;
- }
- void setLibcallName(ArrayRef<RTLIB::Libcall> Calls, const char *Name) {
- for (auto Call : Calls)
- setLibcallName(Call, Name);
- }
-
- const char *getLibcallName(RTLIB::Libcall Call) const {
- return LibcallRoutineNames[Call];
- }
-
-
- void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
- CmpLibcallCCs[Call] = CC;
- }
-
-
- ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
- return CmpLibcallCCs[Call];
- }
-
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
- LibcallCallingConvs[Call] = CC;
- }
-
- CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
- return LibcallCallingConvs[Call];
- }
-
-
-
-
- virtual void finalizeLowering(MachineFunction &MF) const;
-
-
-
-
- virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const;
- private:
- const TargetMachine &TM;
-
-
-
-
-
- bool HasMultipleConditionRegisters;
-
-
-
-
- bool HasExtractBitsInsn;
-
-
-
-
- DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
-
-
-
- bool JumpIsExpensive;
-
-
- BooleanContent BooleanContents;
-
-
- BooleanContent BooleanFloatContents;
-
-
- BooleanContent BooleanVectorContents;
-
-
- Sched::Preference SchedPreferenceInfo;
-
- Align MinStackArgumentAlignment;
-
-
- Align MinFunctionAlignment;
-
-
- Align PrefFunctionAlignment;
-
- Align PrefLoopAlignment;
-
- unsigned MaxBytesForAlignment;
-
-
- unsigned MaxAtomicSizeInBitsSupported;
-
-
- unsigned MaxDivRemBitWidthSupported;
-
-
- unsigned MaxLargeFPConvertBitWidthSupported;
-
-
- unsigned MinCmpXchgSizeInBits;
-
- bool SupportsUnalignedAtomics;
-
-
- Register StackPointerRegisterToSaveRestore;
-
-
- const TargetRegisterClass *RegClassForVT[MVT::VALUETYPE_SIZE];
- uint16_t NumRegistersForVT[MVT::VALUETYPE_SIZE];
- MVT RegisterTypeForVT[MVT::VALUETYPE_SIZE];
-
-
-
-
-
-
- const TargetRegisterClass *RepRegClassForVT[MVT::VALUETYPE_SIZE];
-
-
-
- uint8_t RepRegClassCostForVT[MVT::VALUETYPE_SIZE];
-
-
-
-
-
- MVT TransformToType[MVT::VALUETYPE_SIZE];
-
-
-
-
-
- LegalizeAction OpActions[MVT::VALUETYPE_SIZE][ISD::BUILTIN_OP_END];
-
-
-
-
- uint16_t LoadExtActions[MVT::VALUETYPE_SIZE][MVT::VALUETYPE_SIZE];
-
-
- LegalizeAction TruncStoreActions[MVT::VALUETYPE_SIZE][MVT::VALUETYPE_SIZE];
-
-
-
-
-
-
- uint16_t IndexedModeActions[MVT::VALUETYPE_SIZE][ISD::LAST_INDEXED_MODE];
-
-
-
-
-
-
- uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::VALUETYPE_SIZE + 7) / 8];
- ValueTypeActionImpl ValueTypeActions;
- private:
-
-
-
- unsigned char
- TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
-
-
-
-
-
-
- std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
- PromoteToType;
-
- const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
-
-
- ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
-
- CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
-
- void InitLibcalls(const Triple &TT);
-
-
- enum IndexedModeActionsBits {
- IMAB_Store = 0,
- IMAB_Load = 4,
- IMAB_MaskedStore = 8,
- IMAB_MaskedLoad = 12
- };
- void setIndexedModeAction(unsigned IdxMode, MVT VT, unsigned Shift,
- LegalizeAction Action) {
- assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
- (unsigned)Action < 0xf && "Table isn't big enough!");
- unsigned Ty = (unsigned)VT.SimpleTy;
- IndexedModeActions[Ty][IdxMode] &= ~(0xf << Shift);
- IndexedModeActions[Ty][IdxMode] |= ((uint16_t)Action) << Shift;
- }
- LegalizeAction getIndexedModeAction(unsigned IdxMode, MVT VT,
- unsigned Shift) const {
- assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
- "Table isn't big enough!");
- unsigned Ty = (unsigned)VT.SimpleTy;
- return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] >> Shift) & 0xf);
- }
- protected:
-
-
-
- virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
-
-
-
-
- unsigned GatherAllAliasesMaxDepth;
-
-
-
-
-
-
-
-
-
-
- unsigned MaxStoresPerMemset;
-
- unsigned MaxStoresPerMemsetOptSize;
-
-
-
-
-
-
-
-
-
-
-
- unsigned MaxStoresPerMemcpy;
-
- unsigned MaxStoresPerMemcpyOptSize;
-
-
-
-
-
- unsigned MaxGluedStoresPerMemcpy = 0;
-
-
-
-
-
-
-
-
-
-
-
- unsigned MaxLoadsPerMemcmp;
-
- unsigned MaxLoadsPerMemcmpOptSize;
-
-
-
-
-
-
-
-
-
-
- unsigned MaxStoresPerMemmove;
-
- unsigned MaxStoresPerMemmoveOptSize;
-
-
- bool PredictableSelectIsExpensive;
-
- bool EnableExtLdPromotion;
-
-
- bool isLegalRC(const TargetRegisterInfo &TRI,
- const TargetRegisterClass &RC) const;
-
-
- MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
- MachineBasicBlock *MBB) const;
- bool IsStrictFPEnabled;
- };
- class TargetLowering : public TargetLoweringBase {
- public:
- struct DAGCombinerInfo;
- struct MakeLibCallOptions;
- TargetLowering(const TargetLowering &) = delete;
- TargetLowering &operator=(const TargetLowering &) = delete;
- explicit TargetLowering(const TargetMachine &TM);
- bool isPositionIndependent() const;
- virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
- FunctionLoweringInfo *FLI,
- LegacyDivergenceAnalysis *DA) const {
- return false;
- }
-
-
-
-
-
-
- virtual bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
- SDValue N1) const {
- return N0.hasOneUse();
- }
- virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
- return false;
- }
-
-
-
- virtual bool getPreIndexedAddressParts(SDNode * , SDValue &,
- SDValue &,
- ISD::MemIndexedMode &,
- SelectionDAG &) const {
- return false;
- }
-
-
-
- virtual bool getPostIndexedAddressParts(SDNode * , SDNode * ,
- SDValue &,
- SDValue &,
- ISD::MemIndexedMode &,
- SelectionDAG &) const {
- return false;
- }
-
-
-
- virtual bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset,
- bool IsPre, MachineRegisterInfo &MRI) const {
- return false;
- }
-
-
- virtual unsigned getJumpTableEncoding() const;
- virtual const MCExpr *
- LowerCustomJumpTableEntry(const MachineJumpTableInfo * ,
- const MachineBasicBlock * , unsigned ,
- MCContext &) const {
- llvm_unreachable("Need to implement this hook if target has custom JTIs");
- }
-
- virtual SDValue getPICJumpTableRelocBase(SDValue Table,
- SelectionDAG &DAG) const;
-
-
- virtual const MCExpr *
- getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
- unsigned JTI, MCContext &Ctx) const;
-
-
- virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
-
-
-
-
-
-
-
-
-
- virtual bool
- isInlineAsmTargetBranch(const SmallVectorImpl<StringRef> &AsmStrs,
- unsigned OpNo) const {
- return false;
- }
- bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
- SDValue &Chain) const;
- void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
- SDValue &NewRHS, ISD::CondCode &CCCode,
- const SDLoc &DL, const SDValue OldLHS,
- const SDValue OldRHS) const;
- void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
- SDValue &NewRHS, ISD::CondCode &CCCode,
- const SDLoc &DL, const SDValue OldLHS,
- const SDValue OldRHS, SDValue &Chain,
- bool IsSignaling = false) const;
-
-
- std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
- EVT RetVT, ArrayRef<SDValue> Ops,
- MakeLibCallOptions CallOptions,
- const SDLoc &dl,
- SDValue Chain = SDValue()) const;
-
-
-
- bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
- const uint32_t *CallerPreservedMask,
- const SmallVectorImpl<CCValAssign> &ArgLocs,
- const SmallVectorImpl<SDValue> &OutVals) const;
-
-
-
-
-
-
- struct TargetLoweringOpt {
- SelectionDAG &DAG;
- bool LegalTys;
- bool LegalOps;
- SDValue Old;
- SDValue New;
- explicit TargetLoweringOpt(SelectionDAG &InDAG,
- bool LT, bool LO) :
- DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
- bool LegalTypes() const { return LegalTys; }
- bool LegalOperations() const { return LegalOps; }
- bool CombineTo(SDValue O, SDValue N) {
- Old = O;
- New = N;
- return true;
- }
- };
-
-
-
-
-
- virtual bool
- findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit,
- const MemOp &Op, unsigned DstAS, unsigned SrcAS,
- const AttributeList &FuncAttributes) const;
-
-
-
-
- bool ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
- const APInt &DemandedElts,
- TargetLoweringOpt &TLO) const;
-
- bool ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
- TargetLoweringOpt &TLO) const;
-
-
-
- virtual bool targetShrinkDemandedConstant(SDValue Op,
- const APInt &DemandedBits,
- const APInt &DemandedElts,
- TargetLoweringOpt &TLO) const {
- return false;
- }
-
-
-
- bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
- TargetLoweringOpt &TLO) const;
-
-
-
-
-
-
-
-
-
-
-
-
-
- bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
- const APInt &DemandedElts, KnownBits &Known,
- TargetLoweringOpt &TLO, unsigned Depth = 0,
- bool AssumeSingleUse = false) const;
-
-
- bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
- KnownBits &Known, TargetLoweringOpt &TLO,
- unsigned Depth = 0,
- bool AssumeSingleUse = false) const;
-
-
- bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
- DAGCombinerInfo &DCI) const;
-
-
- bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
- const APInt &DemandedElts,
- DAGCombinerInfo &DCI) const;
-
-
-
- SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
- const APInt &DemandedElts,
- SelectionDAG &DAG,
- unsigned Depth = 0) const;
-
-
- SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
- SelectionDAG &DAG,
- unsigned Depth = 0) const;
-
-
- SDValue SimplifyMultipleUseDemandedVectorElts(SDValue Op,
- const APInt &DemandedElts,
- SelectionDAG &DAG,
- unsigned Depth = 0) const;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
- APInt &KnownUndef, APInt &KnownZero,
- TargetLoweringOpt &TLO, unsigned Depth = 0,
- bool AssumeSingleUse = false) const;
-
-
- bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
- DAGCombinerInfo &DCI) const;
-
-
- virtual bool
- shouldSimplifyDemandedVectorElts(SDValue Op,
- const TargetLoweringOpt &TLO) const {
- return true;
- }
-
-
-
-
- virtual void computeKnownBitsForTargetNode(const SDValue Op,
- KnownBits &Known,
- const APInt &DemandedElts,
- const SelectionDAG &DAG,
- unsigned Depth = 0) const;
-
-
-
-
- virtual void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis,
- Register R, KnownBits &Known,
- const APInt &DemandedElts,
- const MachineRegisterInfo &MRI,
- unsigned Depth = 0) const;
-
-
-
-
- virtual Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis,
- Register R,
- const MachineRegisterInfo &MRI,
- unsigned Depth = 0) const;
-
-
-
- virtual void computeKnownBitsForFrameIndex(int FIOp,
- KnownBits &Known,
- const MachineFunction &MF) const;
-
-
-
-
- virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
- const APInt &DemandedElts,
- const SelectionDAG &DAG,
- unsigned Depth = 0) const;
-
-
-
-
- virtual unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis,
- Register R,
- const APInt &DemandedElts,
- const MachineRegisterInfo &MRI,
- unsigned Depth = 0) const;
-
-
-
-
-
- virtual bool SimplifyDemandedVectorEltsForTargetNode(
- SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
- APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
-
-
-
-
-
- virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
- const APInt &DemandedBits,
- const APInt &DemandedElts,
- KnownBits &Known,
- TargetLoweringOpt &TLO,
- unsigned Depth = 0) const;
-
-
-
- virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode(
- SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
- SelectionDAG &DAG, unsigned Depth) const;
-
-
-
- virtual bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(
- SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
- bool PoisonOnly, unsigned Depth) const;
-
-
-
- virtual bool
- canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts,
- const SelectionDAG &DAG, bool PoisonOnly,
- bool ConsiderFlags, unsigned Depth) const;
-
-
-
-
- SDValue buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
- SDValue N1, MutableArrayRef<int> Mask,
- SelectionDAG &DAG) const;
-
-
- virtual const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const;
-
-
-
- virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
- const SelectionDAG &DAG,
- bool SNaN = false,
- unsigned Depth = 0) const;
-
-
- virtual bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts,
- APInt &UndefElts,
- const SelectionDAG &DAG,
- unsigned Depth = 0) const;
-
-
- virtual bool isTargetCanonicalConstantNode(SDValue Op) const {
- return Op.getOpcode() == ISD::SPLAT_VECTOR;
- }
- struct DAGCombinerInfo {
- void *DC;
- CombineLevel Level;
- bool CalledByLegalizer;
- public:
- SelectionDAG &DAG;
- DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
- : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
- bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
- bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
- bool isAfterLegalizeDAG() const { return Level >= AfterLegalizeDAG; }
- CombineLevel getDAGCombineLevel() { return Level; }
- bool isCalledByLegalizer() const { return CalledByLegalizer; }
- void AddToWorklist(SDNode *N);
- SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
- SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
- SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
- bool recursivelyDeleteUnusedNodes(SDNode *N);
- void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
- };
-
-
- bool isConstTrueVal(SDValue N) const;
-
-
- bool isConstFalseVal(SDValue N) const;
-
- bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
-
-
- SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
- bool foldBooleans, DAGCombinerInfo &DCI,
- const SDLoc &dl) const;
-
- virtual SDValue unwrapAddress(SDValue N) const { return N; }
-
-
- virtual bool
- isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
-
-
-
-
-
-
-
-
-
-
-
-
-
- virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
-
-
-
-
-
-
-
-
- virtual bool isDesirableToCommuteWithShift(const SDNode *N,
- CombineLevel Level) const {
- return true;
- }
-
-
-
-
- virtual bool isDesirableToCommuteXorWithShift(const SDNode *N) const {
- return true;
- }
-
-
-
-
- virtual bool isTypeDesirableForOp(unsigned , EVT VT) const {
-
- return isTypeLegal(VT);
- }
-
-
-
- virtual bool isDesirableToTransformToIntegerOp(unsigned ,
- EVT ) const {
- return false;
- }
-
-
-
- virtual bool IsDesirableToPromoteOp(SDValue , EVT &) const {
- return false;
- }
-
-
- virtual bool supportSwiftError() const {
- return false;
- }
-
-
- virtual bool supportSplitCSR(MachineFunction *MF) const {
- return false;
- }
-
- virtual bool supportKCFIBundles() const { return false; }
-
-
-
- virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
- llvm_unreachable("Not Implemented");
- }
-
-
-
-
- virtual void insertCopiesSplitCSR(
- MachineBasicBlock *Entry,
- const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
- llvm_unreachable("Not Implemented");
- }
-
-
-
- virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
- bool LegalOps, bool OptForSize,
- NegatibleCost &Cost,
- unsigned Depth = 0) const;
- SDValue getCheaperOrNeutralNegatedExpression(
- SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize,
- const NegatibleCost CostThreshold = NegatibleCost::Neutral,
- unsigned Depth = 0) const {
- NegatibleCost Cost = NegatibleCost::Expensive;
- SDValue Neg =
- getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
- if (!Neg)
- return SDValue();
- if (Cost <= CostThreshold)
- return Neg;
-
- if (Neg->use_empty())
- DAG.RemoveDeadNode(Neg.getNode());
- return SDValue();
- }
-
-
- SDValue getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG,
- bool LegalOps, bool OptForSize,
- unsigned Depth = 0) const {
- return getCheaperOrNeutralNegatedExpression(Op, DAG, LegalOps, OptForSize,
- NegatibleCost::Cheaper, Depth);
- }
-
-
- SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
- bool OptForSize, unsigned Depth = 0) const {
- NegatibleCost Cost = NegatibleCost::Expensive;
- return getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth);
- }
-
-
-
-
-
-
- virtual bool splitValueIntoRegisterParts(
- SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
- unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
- return false;
- }
-
-
-
-
-
-
-
-
-
-
- virtual bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
- const TargetRegisterInfo *TRI,
- const TargetInstrInfo *TII,
- unsigned &PhysReg, int &Cost) const {
- return false;
- }
-
- virtual SDValue
- joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
- const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT,
- std::optional<CallingConv::ID> CC) const {
- return SDValue();
- }
-
-
-
-
- virtual SDValue LowerFormalArguments(
- SDValue , CallingConv::ID , bool ,
- const SmallVectorImpl<ISD::InputArg> & , const SDLoc & ,
- SelectionDAG & , SmallVectorImpl<SDValue> & ) const {
- llvm_unreachable("Not Implemented");
- }
-
-
-
-
- struct CallLoweringInfo {
- SDValue Chain;
- Type *RetTy = nullptr;
- bool RetSExt : 1;
- bool RetZExt : 1;
- bool IsVarArg : 1;
- bool IsInReg : 1;
- bool DoesNotReturn : 1;
- bool IsReturnValueUsed : 1;
- bool IsConvergent : 1;
- bool IsPatchPoint : 1;
- bool IsPreallocated : 1;
- bool NoMerge : 1;
-
-
- bool IsTailCall = false;
-
- bool IsPostTypeLegalization = false;
- unsigned NumFixedArgs = -1;
- CallingConv::ID CallConv = CallingConv::C;
- SDValue Callee;
- ArgListTy Args;
- SelectionDAG &DAG;
- SDLoc DL;
- const CallBase *CB = nullptr;
- SmallVector<ISD::OutputArg, 32> Outs;
- SmallVector<SDValue, 32> OutVals;
- SmallVector<ISD::InputArg, 32> Ins;
- SmallVector<SDValue, 4> InVals;
- const ConstantInt *CFIType = nullptr;
- CallLoweringInfo(SelectionDAG &DAG)
- : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
- DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
- IsPatchPoint(false), IsPreallocated(false), NoMerge(false),
- DAG(DAG) {}
- CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
- DL = dl;
- return *this;
- }
- CallLoweringInfo &setChain(SDValue InChain) {
- Chain = InChain;
- return *this;
- }
-
- CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
- SDValue Target, ArgListTy &&ArgsList) {
- RetTy = ResultType;
- Callee = Target;
- CallConv = CC;
- NumFixedArgs = ArgsList.size();
- Args = std::move(ArgsList);
- DAG.getTargetLoweringInfo().markLibCallAttributes(
- &(DAG.getMachineFunction()), CC, Args);
- return *this;
- }
- CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
- SDValue Target, ArgListTy &&ArgsList) {
- RetTy = ResultType;
- Callee = Target;
- CallConv = CC;
- NumFixedArgs = ArgsList.size();
- Args = std::move(ArgsList);
- return *this;
- }
- CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
- SDValue Target, ArgListTy &&ArgsList,
- const CallBase &Call) {
- RetTy = ResultType;
- IsInReg = Call.hasRetAttr(Attribute::InReg);
- DoesNotReturn =
- Call.doesNotReturn() ||
- (!isa<InvokeInst>(Call) && isa<UnreachableInst>(Call.getNextNode()));
- IsVarArg = FTy->isVarArg();
- IsReturnValueUsed = !Call.use_empty();
- RetSExt = Call.hasRetAttr(Attribute::SExt);
- RetZExt = Call.hasRetAttr(Attribute::ZExt);
- NoMerge = Call.hasFnAttr(Attribute::NoMerge);
- Callee = Target;
- CallConv = Call.getCallingConv();
- NumFixedArgs = FTy->getNumParams();
- Args = std::move(ArgsList);
- CB = &Call;
- return *this;
- }
- CallLoweringInfo &setInRegister(bool Value = true) {
- IsInReg = Value;
- return *this;
- }
- CallLoweringInfo &setNoReturn(bool Value = true) {
- DoesNotReturn = Value;
- return *this;
- }
- CallLoweringInfo &setVarArg(bool Value = true) {
- IsVarArg = Value;
- return *this;
- }
- CallLoweringInfo &setTailCall(bool Value = true) {
- IsTailCall = Value;
- return *this;
- }
- CallLoweringInfo &setDiscardResult(bool Value = true) {
- IsReturnValueUsed = !Value;
- return *this;
- }
- CallLoweringInfo &setConvergent(bool Value = true) {
- IsConvergent = Value;
- return *this;
- }
- CallLoweringInfo &setSExtResult(bool Value = true) {
- RetSExt = Value;
- return *this;
- }
- CallLoweringInfo &setZExtResult(bool Value = true) {
- RetZExt = Value;
- return *this;
- }
- CallLoweringInfo &setIsPatchPoint(bool Value = true) {
- IsPatchPoint = Value;
- return *this;
- }
- CallLoweringInfo &setIsPreallocated(bool Value = true) {
- IsPreallocated = Value;
- return *this;
- }
- CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
- IsPostTypeLegalization = Value;
- return *this;
- }
- CallLoweringInfo &setCFIType(const ConstantInt *Type) {
- CFIType = Type;
- return *this;
- }
- ArgListTy &getArgs() {
- return Args;
- }
- };
-
- struct MakeLibCallOptions {
-
-
- ArrayRef<EVT> OpsVTBeforeSoften;
- EVT RetVTBeforeSoften;
- bool IsSExt : 1;
- bool DoesNotReturn : 1;
- bool IsReturnValueUsed : 1;
- bool IsPostTypeLegalization : 1;
- bool IsSoften : 1;
- MakeLibCallOptions()
- : IsSExt(false), DoesNotReturn(false), IsReturnValueUsed(true),
- IsPostTypeLegalization(false), IsSoften(false) {}
- MakeLibCallOptions &setSExt(bool Value = true) {
- IsSExt = Value;
- return *this;
- }
- MakeLibCallOptions &setNoReturn(bool Value = true) {
- DoesNotReturn = Value;
- return *this;
- }
- MakeLibCallOptions &setDiscardResult(bool Value = true) {
- IsReturnValueUsed = !Value;
- return *this;
- }
- MakeLibCallOptions &setIsPostTypeLegalization(bool Value = true) {
- IsPostTypeLegalization = Value;
- return *this;
- }
- MakeLibCallOptions &setTypeListBeforeSoften(ArrayRef<EVT> OpsVT, EVT RetVT,
- bool Value = true) {
- OpsVTBeforeSoften = OpsVT;
- RetVTBeforeSoften = RetVT;
- IsSoften = Value;
- return *this;
- }
- };
-
-
-
-
- std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
-
-
-
-
-
- virtual SDValue
- LowerCall(CallLoweringInfo &,
- SmallVectorImpl<SDValue> &) const {
- llvm_unreachable("Not Implemented");
- }
-
- virtual void HandleByVal(CCState *, unsigned &, Align) const {}
-
-
-
- virtual bool CanLowerReturn(CallingConv::ID ,
- MachineFunction &, bool ,
- const SmallVectorImpl<ISD::OutputArg> &,
- LLVMContext &) const
- {
-
- return true;
- }
-
-
-
- virtual SDValue LowerReturn(SDValue , CallingConv::ID ,
- bool ,
- const SmallVectorImpl<ISD::OutputArg> & ,
- const SmallVectorImpl<SDValue> & ,
- const SDLoc & ,
- SelectionDAG & ) const {
- llvm_unreachable("Not Implemented");
- }
-
-
-
-
-
- virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const {
- return false;
- }
-
-
-
- virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
- return false;
- }
-
-
- virtual const char * getClearCacheBuiltinName() const {
- return "__clear_cache";
- }
-
-
-
- virtual Register getRegisterByName(const char* RegName, LLT Ty,
- const MachineFunction &MF) const {
- report_fatal_error("Named registers not implemented for this target");
- }
-
-
-
-
-
-
- virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
- ISD::NodeType ) const {
- EVT MinVT = getRegisterType(Context, MVT::i32);
- return VT.bitsLT(MinVT) ? MinVT : VT;
- }
-
-
-
- virtual bool
- functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
- bool isVarArg,
- const DataLayout &DL) const {
- return false;
- }
-
-
-
-
- virtual bool
- shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const {
- return DL.isLittleEndian();
- }
-
-
- virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
- return nullptr;
- }
-
-
-
-
-
-
-
- virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
- SelectionDAG &DAG) const {
- return Chain;
- }
-
-
-
-
- virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const {
- assert(SI.isAtomic() && "violated precondition");
- return false;
- }
-
-
-
-
- virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const {
- assert(LI.isAtomic() && "violated precondition");
- return false;
- }
-
-
-
-
-
-
-
-
-
-
-
-
-
- virtual void LowerOperationWrapper(SDNode *N,
- SmallVectorImpl<SDValue> &Results,
- SelectionDAG &DAG) const;
-
-
-
-
-
- virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
-
-
-
-
-
-
-
-
-
- virtual void ReplaceNodeResults(SDNode * ,
- SmallVectorImpl<SDValue> &,
- SelectionDAG &) const {
- llvm_unreachable("ReplaceNodeResults not implemented for this target!");
- }
-
- virtual const char *getTargetNodeName(unsigned Opcode) const;
-
-
- virtual FastISel *createFastISel(FunctionLoweringInfo &,
- const TargetLibraryInfo *) const {
- return nullptr;
- }
- bool verifyReturnAddressArgumentIsConstant(SDValue Op,
- SelectionDAG &DAG) const;
-
-
-
-
-
-
-
- virtual bool ExpandInlineAsm(CallInst *) const {
- return false;
- }
- enum ConstraintType {
- C_Register,
- C_RegisterClass,
- C_Memory,
- C_Address,
- C_Immediate,
- C_Other,
- C_Unknown
- };
- enum ConstraintWeight {
-
- CW_Invalid = -1,
- CW_Okay = 0,
- CW_Good = 1,
- CW_Better = 2,
- CW_Best = 3,
-
- CW_SpecificReg = CW_Okay,
- CW_Register = CW_Good,
- CW_Memory = CW_Better,
- CW_Constant = CW_Best,
- CW_Default = CW_Okay
- };
-
- struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
-
-
-
- std::string ConstraintCode;
-
-
- TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
-
-
-
- Value *CallOperandVal = nullptr;
-
- MVT ConstraintVT = MVT::Other;
-
- AsmOperandInfo(InlineAsm::ConstraintInfo Info)
- : InlineAsm::ConstraintInfo(std::move(Info)) {}
-
-
- bool isMatchingInputConstraint() const;
-
-
- unsigned getMatchedOperand() const;
- };
- using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
-
-
-
-
- virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
- const TargetRegisterInfo *TRI,
- const CallBase &Call) const;
-
-
- virtual ConstraintWeight getMultipleConstraintMatchWeight(
- AsmOperandInfo &info, int maIndex) const;
-
-
- virtual ConstraintWeight getSingleConstraintMatchWeight(
- AsmOperandInfo &info, const char *constraint) const;
-
-
-
-
- virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
- SDValue Op,
- SelectionDAG *DAG = nullptr) const;
-
- virtual ConstraintType getConstraintType(StringRef Constraint) const;
-
-
-
-
-
-
-
-
-
- virtual std::pair<unsigned, const TargetRegisterClass *>
- getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
- StringRef Constraint, MVT VT) const;
- virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
- if (ConstraintCode == "m")
- return InlineAsm::Constraint_m;
- if (ConstraintCode == "o")
- return InlineAsm::Constraint_o;
- if (ConstraintCode == "X")
- return InlineAsm::Constraint_X;
- if (ConstraintCode == "p")
- return InlineAsm::Constraint_p;
- return InlineAsm::Constraint_Unknown;
- }
-
-
-
- virtual const char *LowerXConstraint(EVT ConstraintVT) const;
-
-
- virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
- std::vector<SDValue> &Ops,
- SelectionDAG &DAG) const;
-
- virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
- const SDLoc &DL,
- const AsmOperandInfo &OpInfo,
- SelectionDAG &DAG) const;
-
-
- virtual void CollectTargetIntrinsicOperands(const CallInst &I,
- SmallVectorImpl<SDValue> &Ops,
- SelectionDAG &DAG) const;
-
-
-
- SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
- SmallVectorImpl<SDNode *> &Created) const;
- SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
- SmallVectorImpl<SDNode *> &Created) const;
-
-
-
-
- virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
- SelectionDAG &DAG,
- SmallVectorImpl<SDNode *> &Created) const;
-
-
-
-
- virtual SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor,
- SelectionDAG &DAG,
- SmallVectorImpl<SDNode *> &Created) const;
-
-
-
-
- virtual unsigned combineRepeatedFPDivisors() const {
- return 0;
- }
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
- int Enabled, int &RefinementSteps,
- bool &UseOneConstNR, bool Reciprocal) const {
- return SDValue();
- }
-
-
-
-
-
- SDValue createSelectForFMINNUM_FMAXNUM(SDNode *Node, SelectionDAG &DAG) const;
-
-
-
-
-
-
-
-
-
-
- virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
- int Enabled, int &RefinementSteps) const {
- return SDValue();
- }
-
-
-
-
- virtual SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,
- const DenormalMode &Mode) const;
-
-
- virtual SDValue getSqrtResultForDenormInput(SDValue Operand,
- SelectionDAG &DAG) const {
- return DAG.getConstantFP(0.0, SDLoc(Operand), Operand.getValueType());
- }
-
-
-
-
-
-
-
-
-
-
-
-
-
- bool expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS,
- SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
- SelectionDAG &DAG, MulExpansionKind Kind,
- SDValue LL = SDValue(), SDValue LH = SDValue(),
- SDValue RL = SDValue(), SDValue RH = SDValue()) const;
-
-
-
-
-
-
-
-
-
- bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
- SelectionDAG &DAG, MulExpansionKind Kind,
- SDValue LL = SDValue(), SDValue LH = SDValue(),
- SDValue RL = SDValue(), SDValue RH = SDValue()) const;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- bool expandDIVREMByConstant(SDNode *N, SmallVectorImpl<SDValue> &Result,
- EVT HiLoVT, SelectionDAG &DAG,
- SDValue LL = SDValue(),
- SDValue LH = SDValue()) const;
-
-
-
- SDValue expandFunnelShift(SDNode *N, SelectionDAG &DAG) const;
-
-
-
-
-
- SDValue expandROT(SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) const;
-
-
-
-
- void expandShiftParts(SDNode *N, SDValue &Lo, SDValue &Hi,
- SelectionDAG &DAG) const;
-
-
-
-
- bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
-
-
-
-
-
- bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain,
- SelectionDAG &DAG) const;
-
-
-
-
-
- bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain,
- SelectionDAG &DAG) const;
-
- SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
-
-
-
- SDValue expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) const;
-
-
-
-
-
-
- SDValue expandIS_FPCLASS(EVT ResultVT, SDValue Op, unsigned Test,
- SDNodeFlags Flags, const SDLoc &DL,
- SelectionDAG &DAG) const;
-
-
-
-
- SDValue expandCTPOP(SDNode *N, SelectionDAG &DAG) const;
-
-
- SDValue expandVPCTPOP(SDNode *N, SelectionDAG &DAG) const;
-
-
-
-
- SDValue expandCTLZ(SDNode *N, SelectionDAG &DAG) const;
-
-
-
- SDValue expandVPCTLZ(SDNode *N, SelectionDAG &DAG) const;
-
-
-
- SDValue CTTZTableLookup(SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT,
- SDValue Op, unsigned NumBitsPerElt) const;
-
-
-
-
- SDValue expandCTTZ(SDNode *N, SelectionDAG &DAG) const;
-
-
-
- SDValue expandVPCTTZ(SDNode *N, SelectionDAG &DAG) const;
-
-
-
-
-
-
- SDValue expandABS(SDNode *N, SelectionDAG &DAG,
- bool IsNegative = false) const;
-
-
-
-
- SDValue expandBSWAP(SDNode *N, SelectionDAG &DAG) const;
-
-
-
- SDValue expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const;
-
-
-
-
- SDValue expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const;
-
-
-
- SDValue expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const;
-
-
-
- std::pair<SDValue, SDValue> scalarizeVectorLoad(LoadSDNode *LD,
- SelectionDAG &DAG) const;
-
-
-
- SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
-
-
- std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
- SelectionDAG &DAG) const;
-
-
- SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
-
-
-
-
-
-
-
- SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
- EVT DataVT, SelectionDAG &DAG,
- bool IsCompressedMemory) const;
-
-
-
-
- SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
- SDValue Index) const;
-
-
-
-
-
- SDValue getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
- EVT SubVecVT, SDValue Index) const;
-
-
- SDValue expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const;
-
-
- SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
-
-
- SDValue expandShlSat(SDNode *Node, SelectionDAG &DAG) const;
-
-
- SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
-
-
-
-
- SDValue expandFixedPointDiv(unsigned Opcode, const SDLoc &dl,
- SDValue LHS, SDValue RHS,
- unsigned Scale, SelectionDAG &DAG) const;
-
-
- void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
- SelectionDAG &DAG) const;
-
-
- void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
- SelectionDAG &DAG) const;
-
-
- bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
- SelectionDAG &DAG) const;
-
-
- SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;
-
- SDValue expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) const;
-
-
- bool expandREM(SDNode *Node, SDValue &Result, SelectionDAG &DAG) const;
-
-
- SDValue expandVectorSplice(SDNode *Node, SelectionDAG &DAG) const;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- bool LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS,
- SDValue &RHS, SDValue &CC, SDValue Mask,
- SDValue EVL, bool &NeedInvert, const SDLoc &dl,
- SDValue &Chain, bool IsSignaling = false) const;
-
-
-
-
-
-
-
-
-
-
-
- virtual MachineBasicBlock *
- EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
-
-
-
-
- virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
- SDNode *Node) const;
-
-
- virtual bool useLoadStackGuardNode() const {
- return false;
- }
- virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
- const SDLoc &DL) const {
- llvm_unreachable("not implemented for this target");
- }
-
- virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
- SelectionDAG &DAG) const;
-
-
- virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
- SelectionDAG &DAG) const {
- return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
- }
-
-
-
-
- SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
- private:
- SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
- const SDLoc &DL, DAGCombinerInfo &DCI) const;
- SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
- const SDLoc &DL, DAGCombinerInfo &DCI) const;
- SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
- SDValue N1, ISD::CondCode Cond,
- DAGCombinerInfo &DCI,
- const SDLoc &DL) const;
-
- SDValue optimizeSetCCByHoistingAndByConstFromLogicalShift(
- EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
- DAGCombinerInfo &DCI, const SDLoc &DL) const;
- SDValue prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
- SDValue CompTargetNode, ISD::CondCode Cond,
- DAGCombinerInfo &DCI, const SDLoc &DL,
- SmallVectorImpl<SDNode *> &Created) const;
- SDValue buildUREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
- ISD::CondCode Cond, DAGCombinerInfo &DCI,
- const SDLoc &DL) const;
- SDValue prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
- SDValue CompTargetNode, ISD::CondCode Cond,
- DAGCombinerInfo &DCI, const SDLoc &DL,
- SmallVectorImpl<SDNode *> &Created) const;
- SDValue buildSREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
- ISD::CondCode Cond, DAGCombinerInfo &DCI,
- const SDLoc &DL) const;
- };
- void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr,
- SmallVectorImpl<ISD::OutputArg> &Outs,
- const TargetLowering &TLI, const DataLayout &DL);
- }
- #endif
- #ifdef __GNUC__
- #pragma GCC diagnostic pop
- #endif
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