Home Explore Help
Sign In
SMusatov
/
ydb
mirror of https://github.com/ydb-platform/ydb.git
1
0
Fork 0
Files
Tree: d7ebb0f351
Branches Tags
ydb
/
contrib
/
libs
/
llvm16
/
lib
/
Target
/
AArch64
/
AArch64SchedA57.td

AArch64SchedA57.td 36 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691 
  1. //=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
    2. 

  2. //
    3. 

  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
    4. 

  4. // See https://llvm.org/LICENSE.txt for license information.
    5. 

  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
    6. 

  6. //
    7. 

  7. //===----------------------------------------------------------------------===//
    8. 

  8. //
    9. 

  9. // This file defines the machine model for ARM Cortex-A57 to support
    10. 

  10. // instruction scheduling and other instruction cost heuristics.
    11. 

  11. //
    12. 

  12. //===----------------------------------------------------------------------===//
    13. 

  13. 

  14. //===----------------------------------------------------------------------===//
    15. 

  15. // The Cortex-A57 is a traditional superscalar microprocessor with a
    16. 

  16. // conservative 3-wide in-order stage for decode and dispatch. Combined with the
    17. 

  17. // much wider out-of-order issue stage, this produced a need to carefully
    18. 

  18. // schedule micro-ops so that all three decoded each cycle are successfully
    19. 

  19. // issued as the reservation station(s) simply don't stay occupied for long.
    20. 

  20. // Therefore, IssueWidth is set to the narrower of the two at three, while still
    21. 

  21. // modeling the machine as out-of-order.
    22. 

  22. 

  23. def CortexA57Model : SchedMachineModel {
    24. 

  24.   let IssueWidth        =   3; // 3-way decode and dispatch
    25. 

  25.   let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
    26. 

  26.   let LoadLatency       =   4; // Optimistic load latency
    27. 

  27.   let MispredictPenalty =  14; // Fetch + Decode/Rename/Dispatch + Branch
    28. 

  28. 

  29.   // Enable partial & runtime unrolling. The magic number is chosen based on
    30. 

  30.   // experiments and benchmarking data.
    31. 

  31.   let LoopMicroOpBufferSize = 16;
    32. 

  32.   let CompleteModel = 1;
    33. 

  33. 

  34.   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
    35. 

  35.                                                     PAUnsupported.F,
    36. 

  36.                                                     SMEUnsupported.F,
    37. 

  37.                                                     [HasMTE]);
    38. 

  38. }
    39. 

  39. 

  40. //===----------------------------------------------------------------------===//
    41. 

  41. // Define each kind of processor resource and number available on Cortex-A57.
    42. 

  42. // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
    43. 

  43. // micro-ops wait for their operands and then issue out-of-order.
    44. 

  44. 

  45. def A57UnitB : ProcResource<1>;  // Type B micro-ops
    46. 

  46. def A57UnitI : ProcResource<2>;  // Type I micro-ops
    47. 

  47. def A57UnitM : ProcResource<1>;  // Type M micro-ops
    48. 

  48. def A57UnitL : ProcResource<1>;  // Type L micro-ops
    49. 

  49. def A57UnitS : ProcResource<1>;  // Type S micro-ops
    50. 

  50. def A57UnitX : ProcResource<1>;  // Type X micro-ops
    51. 

  51. def A57UnitW : ProcResource<1>;  // Type W micro-ops
    52. 

  52. let SchedModel = CortexA57Model in {
    53. 

  53.   def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>;    // Type V micro-ops
    54. 

  54. }
    55. 

  55. 

  56. let SchedModel = CortexA57Model in {
    57. 

  57. 

  58. //===----------------------------------------------------------------------===//
    59. 

  59. // Define customized scheduler read/write types specific to the Cortex-A57.
    60. 

  60. 

  61. include "AArch64SchedA57WriteRes.td"
    62. 

  62. 

  63. //===----------------------------------------------------------------------===//
    64. 

  64. // Map the target-defined scheduler read/write resources and latency for
    65. 

  65. // Cortex-A57. The Cortex-A57 types are directly associated with resources, so
    66. 

  66. // defining the aliases precludes the need for mapping them using WriteRes. The
    67. 

  67. // aliases are sufficient for creating a coarse, working model. As the model
    68. 

  68. // evolves, InstRWs will be used to override some of these SchedAliases.
    69. 

  69. //
    70. 

  70. // WARNING: Using SchedAliases is convenient and works well for latency and
    71. 

  71. //          resource lookup for instructions. However, this creates an entry in
    72. 

  72. //          AArch64WriteLatencyTable with a WriteResourceID of 0, breaking
    73. 

  73. //          any SchedReadAdvance since the lookup will fail.
    74. 

  74. 

  75. def : SchedAlias<WriteImm,   A57Write_1cyc_1I>;
    76. 

  76. def : SchedAlias<WriteI,     A57Write_1cyc_1I>;
    77. 

  77. def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
    78. 

  78. def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
    79. 

  79. def : SchedAlias<WriteExtr,  A57Write_1cyc_1I>;
    80. 

  80. def : SchedAlias<WriteIS,    A57Write_1cyc_1I>;
    81. 

  81. def : SchedAlias<WriteID32,  A57Write_19cyc_1M>;
    82. 

  82. def : SchedAlias<WriteID64,  A57Write_35cyc_1M>;
    83. 

  83. def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; }
    84. 

  84. def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; }
    85. 

  85. def : SchedAlias<WriteBr,    A57Write_1cyc_1B>;
    86. 

  86. def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
    87. 

  87. def : SchedAlias<WriteLD,    A57Write_4cyc_1L>;
    88. 

  88. def : SchedAlias<WriteST,    A57Write_1cyc_1S>;
    89. 

  89. def : SchedAlias<WriteSTP,   A57Write_1cyc_1S>;
    90. 

  90. def : SchedAlias<WriteAdr,   A57Write_1cyc_1I>;
    91. 

  91. def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
    92. 

  92. def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;
    93. 

  93. def : SchedAlias<WriteF,     A57Write_3cyc_1V>;
    94. 

  94. def : SchedAlias<WriteFCmp,  A57Write_3cyc_1V>;
    95. 

  95. def : SchedAlias<WriteFCvt,  A57Write_5cyc_1V>;
    96. 

  96. def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>;
    97. 

  97. def : SchedAlias<WriteFImm,  A57Write_3cyc_1V>;
    98. 

  98. def : WriteRes<WriteFMul, [A57UnitV]> { let Latency = 5;}
    99. 

  99. def : SchedAlias<WriteFDiv,  A57Write_17cyc_1W>;
    100. 

  100. def : SchedAlias<WriteVd,    A57Write_3cyc_1V>;
    101. 

  101. def : SchedAlias<WriteVq,    A57Write_3cyc_1V>;
    102. 

  102. def : SchedAlias<WriteVLD,   A57Write_5cyc_1L>;
    103. 

  103. def : SchedAlias<WriteVST,   A57Write_1cyc_1S>;
    104. 

  104. 

  105. def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
    106. 

  106. 

  107. def : WriteRes<WriteSys,     []> { let Latency = 1; }
    108. 

  108. def : WriteRes<WriteBarrier, []> { let Latency = 1; }
    109. 

  109. def : WriteRes<WriteHint,    []> { let Latency = 1; }
    110. 

  110. 

  111. def : WriteRes<WriteLDHi,    []> { let Latency = 4; }
    112. 

  112. 

  113. // Forwarding logic is only modeled for multiply and accumulate
    114. 

  114. def : ReadAdvance<ReadI,       0>;
    115. 

  115. def : ReadAdvance<ReadISReg,   0>;
    116. 

  116. def : ReadAdvance<ReadIEReg,   0>;
    117. 

  117. def : ReadAdvance<ReadIM,      0>;
    118. 

  118. def : ReadAdvance<ReadIMA,     2, [WriteIM32, WriteIM64]>;
    119. 

  119. def : ReadAdvance<ReadID,      0>;
    120. 

  120. def : ReadAdvance<ReadExtrHi,  0>;
    121. 

  121. def : ReadAdvance<ReadST,      0>;
    122. 

  122. def : ReadAdvance<ReadAdrBase, 0>;
    123. 

  123. def : ReadAdvance<ReadVLD,     0>;
    124. 

  124. 

  125. 

  126. //===----------------------------------------------------------------------===//
    127. 

  127. // Specialize the coarse model by associating instruction groups with the
    128. 

  128. // subtarget-defined types. As the modeled is refined, this will override most
    129. 

  129. // of the above ShchedAlias mappings.
    130. 

  130. 

  131. // Miscellaneous
    132. 

  132. // -----------------------------------------------------------------------------
    133. 

  133. 

  134. def : InstRW<[WriteI], (instrs COPY)>;
    135. 

  135. 

  136. 

  137. // Branch Instructions
    138. 

  138. // -----------------------------------------------------------------------------
    139. 

  139. 

  140. def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
    141. 

  141. def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
    142. 

  142. 

  143. 

  144. // Shifted Register with Shift == 0
    145. 

  145. // ----------------------------------------------------------------------------
    146. 

  146. 

  147. def A57WriteISReg : SchedWriteVariant<[
    148. 

  148.        SchedVar<RegShiftedPred, [WriteISReg]>,
    149. 

  149.        SchedVar<NoSchedPred, [WriteI]>]>;
    150. 

  150. def : InstRW<[A57WriteISReg], (instregex ".*rs$")>;
    151. 

  151. 

  152. 

  153. // Divide and Multiply Instructions
    154. 

  154. // -----------------------------------------------------------------------------
    155. 

  155. 

  156. // Multiply high
    157. 

  157. def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
    158. 

  158. 

  159. 

  160. // Miscellaneous Data-Processing Instructions
    161. 

  161. // -----------------------------------------------------------------------------
    162. 

  162. 

  163. def : InstRW<[A57Write_1cyc_1I],    (instrs EXTRWrri)>;
    164. 

  164. def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
    165. 

  165. def : InstRW<[A57Write_2cyc_1M],    (instregex "BFM")>;
    166. 

  166. 

  167. 

  168. // Cryptography Extensions
    169. 

  169. // -----------------------------------------------------------------------------
    170. 

  170. 

  171. def A57ReadAES  : SchedReadAdvance<3, [A57Write_3cyc_1W]>;
    172. 

  172. def : InstRW<[A57Write_3cyc_1W], (instregex "^AES[DE]")>;
    173. 

  173. def : InstRW<[A57Write_3cyc_1W, A57ReadAES], (instregex "^AESI?MC")>;
    174. 

  174. def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>;
    175. 

  175. def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>;
    176. 

  176. def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>;
    177. 

  177. def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>;
    178. 

  178. def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>;
    179. 

  179. def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>;
    180. 

  180. 

  181. 

  182. // Vector Load
    183. 

  183. // -----------------------------------------------------------------------------
    184. 

  184. 

  185. def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1i(8|16|32)$")>;
    186. 

  186. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
    187. 

  187. def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1i(64)$")>;
    188. 

  188. def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1i(64)_POST$")>;
    189. 

  189. 

  190. def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(8b|4h|2s)$")>;
    191. 

  191. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
    192. 

  192. def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1Rv(1d)$")>;
    193. 

  193. def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1Rv(1d)_POST$")>;
    194. 

  194. def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(16b|8h|4s|2d)$")>;
    195. 

  195. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
    196. 

  196. 

  197. def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(8b|4h|2s|1d)$")>;
    198. 

  198. def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
    199. 

  199. def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(16b|8h|4s|2d)$")>;
    200. 

  200. def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
    201. 

  201. def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Twov(8b|4h|2s|1d)$")>;
    202. 

  202. def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
    203. 

  203. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Twov(16b|8h|4s|2d)$")>;
    204. 

  204. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
    205. 

  205. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Threev(8b|4h|2s|1d)$")>;
    206. 

  206. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
    207. 

  207. def : InstRW<[A57Write_7cyc_3L],            (instregex "LD1Threev(16b|8h|4s|2d)$")>;
    208. 

  208. def : InstRW<[A57Write_7cyc_3L, WriteAdr],  (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
    209. 

  209. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
    210. 

  210. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
    211. 

  211. def : InstRW<[A57Write_8cyc_4L],           (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
    212. 

  212. def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
    213. 

  213. 

  214. def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2i(8|16)$")>;
    215. 

  215. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>;
    216. 

  216. def : InstRW<[A57Write_6cyc_2L],            (instregex "LD2i(32)$")>;
    217. 

  217. def : InstRW<[A57Write_6cyc_2L, WriteAdr],  (instregex "LD2i(32)_POST$")>;
    218. 

  218. def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2i(64)$")>;
    219. 

  219. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2i(64)_POST$")>;
    220. 

  220. 

  221. def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2Rv(8b|4h|2s)$")>;
    222. 

  222. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2Rv(8b|4h|2s)_POST$")>;
    223. 

  223. def : InstRW<[A57Write_5cyc_1L],             (instregex "LD2Rv(1d)$")>;
    224. 

  224. def : InstRW<[A57Write_5cyc_1L, WriteAdr],   (instregex "LD2Rv(1d)_POST$")>;
    225. 

  225. def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2Rv(16b|8h|4s|2d)$")>;
    226. 

  226. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
    227. 

  227. 

  228. def : InstRW<[A57Write_8cyc_1L_1V],             (instregex "LD2Twov(8b|4h|2s)$")>;
    229. 

  229. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],   (instregex "LD2Twov(8b|4h|2s)_POST$")>;
    230. 

  230. def : InstRW<[A57Write_9cyc_2L_2V],           (instregex "LD2Twov(16b|8h|4s)$")>;
    231. 

  231. def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
    232. 

  232. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD2Twov(2d)$")>;
    233. 

  233. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD2Twov(2d)_POST$")>;
    234. 

  234. 

  235. def : InstRW<[A57Write_9cyc_1L_3V],           (instregex "LD3i(8|16)$")>;
    236. 

  236. def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>;
    237. 

  237. def : InstRW<[A57Write_8cyc_1L_2V],            (instregex "LD3i(32)$")>;
    238. 

  238. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],  (instregex "LD3i(32)_POST$")>;
    239. 

  239. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD3i(64)$")>;
    240. 

  240. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD3i(64)_POST$")>;
    241. 

  241. 

  242. def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD3Rv(8b|4h|2s)$")>;
    243. 

  243. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD3Rv(8b|4h|2s)_POST$")>;
    244. 

  244. def : InstRW<[A57Write_6cyc_2L],              (instregex "LD3Rv(1d)$")>;
    245. 

  245. def : InstRW<[A57Write_6cyc_2L, WriteAdr],    (instregex "LD3Rv(1d)_POST$")>;
    246. 

  246. def : InstRW<[A57Write_9cyc_1L_3V],            (instregex "LD3Rv(16b|8h|4s)$")>;
    247. 

  247. def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr],  (instregex "LD3Rv(16b|8h|4s)_POST$")>;
    248. 

  248. def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD3Rv(2d)$")>;
    249. 

  249. def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
    250. 

  250. 

  251. def : InstRW<[A57Write_9cyc_2L_2V],               (instregex "LD3Threev(8b|4h|2s)$")>;
    252. 

  252. def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],     (instregex "LD3Threev(8b|4h|2s)_POST$")>;
    253. 

  253. def : InstRW<[A57Write_10cyc_3L_4V],           (instregex "LD3Threev(16b|8h|4s)$")>;
    254. 

  254. def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
    255. 

  255. def : InstRW<[A57Write_8cyc_4L],               (instregex "LD3Threev(2d)$")>;
    256. 

  256. def : InstRW<[A57Write_8cyc_4L, WriteAdr],     (instregex "LD3Threev(2d)_POST$")>;
    257. 

  257. 

  258. def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(8|16)$")>;
    259. 

  259. def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>;
    260. 

  260. def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD4i(32)$")>;
    261. 

  261. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD4i(32)_POST$")>;
    262. 

  262. def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(64)$")>;
    263. 

  263. def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>;
    264. 

  264. 

  265. def : InstRW<[A57Write_8cyc_1L_2V],              (instregex "LD4Rv(8b|4h|2s)$")>;
    266. 

  266. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],    (instregex "LD4Rv(8b|4h|2s)_POST$")>;
    267. 

  267. def : InstRW<[A57Write_6cyc_2L],               (instregex "LD4Rv(1d)$")>;
    268. 

  268. def : InstRW<[A57Write_6cyc_2L, WriteAdr],     (instregex "LD4Rv(1d)_POST$")>;
    269. 

  269. def : InstRW<[A57Write_9cyc_2L_3V],            (instregex "LD4Rv(16b|8h|4s)$")>;
    270. 

  270. def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr],  (instregex "LD4Rv(16b|8h|4s)_POST$")>;
    271. 

  271. def : InstRW<[A57Write_9cyc_2L_4V],           (instregex "LD4Rv(2d)$")>;
    272. 

  272. def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
    273. 

  273. 

  274. def : InstRW<[A57Write_9cyc_2L_2V],                (instregex "LD4Fourv(8b|4h|2s)$")>;
    275. 

  275. def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],      (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
    276. 

  276. def : InstRW<[A57Write_11cyc_4L_4V],           (instregex "LD4Fourv(16b|8h|4s)$")>;
    277. 

  277. def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
    278. 

  278. def : InstRW<[A57Write_8cyc_4L],                (instregex "LD4Fourv(2d)$")>;
    279. 

  279. def : InstRW<[A57Write_8cyc_4L, WriteAdr],      (instregex "LD4Fourv(2d)_POST$")>;
    280. 

  280. 

  281. // Vector Store
    282. 

  282. // -----------------------------------------------------------------------------
    283. 

  283. 

  284. def : InstRW<[A57Write_1cyc_1S],            (instregex "ST1i(8|16|32)$")>;
    285. 

  285. def : InstRW<[A57Write_1cyc_1S, WriteAdr],  (instregex "ST1i(8|16|32)_POST$")>;
    286. 

  286. def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST1i(64)$")>;
    287. 

  287. def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>;
    288. 

  288. 

  289. def : InstRW<[A57Write_1cyc_1S],                  (instregex "ST1Onev(8b|4h|2s|1d)$")>;
    290. 

  290. def : InstRW<[A57Write_1cyc_1S, WriteAdr],        (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
    291. 

  291. def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Onev(16b|8h|4s|2d)$")>;
    292. 

  292. def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
    293. 

  293. def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Twov(8b|4h|2s|1d)$")>;
    294. 

  294. def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
    295. 

  295. def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Twov(16b|8h|4s|2d)$")>;
    296. 

  296. def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
    297. 

  297. def : InstRW<[A57Write_3cyc_3S],                (instregex "ST1Threev(8b|4h|2s|1d)$")>;
    298. 

  298. def : InstRW<[A57Write_3cyc_3S, WriteAdr],      (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
    299. 

  299. def : InstRW<[A57Write_6cyc_6S],             (instregex "ST1Threev(16b|8h|4s|2d)$")>;
    300. 

  300. def : InstRW<[A57Write_6cyc_6S, WriteAdr],   (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
    301. 

  301. def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
    302. 

  302. def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
    303. 

  303. def : InstRW<[A57Write_8cyc_8S],           (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
    304. 

  304. def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
    305. 

  305. 

  306. def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST2i(8|16|32)$")>;
    307. 

  307. def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
    308. 

  308. def : InstRW<[A57Write_2cyc_2S],           (instregex "ST2i(64)$")>;
    309. 

  309. def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>;
    310. 

  310. 

  311. def : InstRW<[A57Write_3cyc_2S_1V],              (instregex "ST2Twov(8b|4h|2s)$")>;
    312. 

  312. def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST$")>;
    313. 

  313. def : InstRW<[A57Write_4cyc_4S_2V],           (instregex "ST2Twov(16b|8h|4s)$")>;
    314. 

  314. def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
    315. 

  315. def : InstRW<[A57Write_4cyc_4S],             (instregex "ST2Twov(2d)$")>;
    316. 

  316. def : InstRW<[A57Write_4cyc_4S, WriteAdr],   (instregex "ST2Twov(2d)_POST$")>;
    317. 

  317. 

  318. def : InstRW<[A57Write_3cyc_1S_1V],            (instregex "ST3i(8|16)$")>;
    319. 

  319. def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],  (instregex "ST3i(8|16)_POST$")>;
    320. 

  320. def : InstRW<[A57Write_3cyc_3S],           (instregex "ST3i(32)$")>;
    321. 

  321. def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>;
    322. 

  322. def : InstRW<[A57Write_3cyc_2S_1V],           (instregex "ST3i(64)$")>;
    323. 

  323. def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>;
    324. 

  324. 

  325. def : InstRW<[A57Write_3cyc_3S_2V],                 (instregex "ST3Threev(8b|4h|2s)$")>;
    326. 

  326. def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr],       (instregex "ST3Threev(8b|4h|2s)_POST$")>;
    327. 

  327. def : InstRW<[A57Write_6cyc_6S_4V],           (instregex "ST3Threev(16b|8h|4s)$")>;
    328. 

  328. def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
    329. 

  329. def : InstRW<[A57Write_6cyc_6S],                (instregex "ST3Threev(2d)$")>;
    330. 

  330. def : InstRW<[A57Write_6cyc_6S, WriteAdr],      (instregex "ST3Threev(2d)_POST$")>;
    331. 

  331. 

  332. def : InstRW<[A57Write_3cyc_1S_1V],             (instregex "ST4i(8|16)$")>;
    333. 

  333. def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],   (instregex "ST4i(8|16)_POST$")>;
    334. 

  334. def : InstRW<[A57Write_4cyc_4S],           (instregex "ST4i(32)$")>;
    335. 

  335. def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>;
    336. 

  336. def : InstRW<[A57Write_3cyc_2S_1V],            (instregex "ST4i(64)$")>;
    337. 

  337. def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],  (instregex "ST4i(64)_POST$")>;
    338. 

  338. 

  339. def : InstRW<[A57Write_4cyc_4S_2V],                  (instregex "ST4Fourv(8b|4h|2s)$")>;
    340. 

  340. def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr],        (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
    341. 

  341. def : InstRW<[A57Write_8cyc_8S_4V],           (instregex "ST4Fourv(16b|8h|4s)$")>;
    342. 

  342. def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
    343. 

  343. def : InstRW<[A57Write_8cyc_8S],                (instregex "ST4Fourv(2d)$")>;
    344. 

  344. def : InstRW<[A57Write_8cyc_8S, WriteAdr],      (instregex "ST4Fourv(2d)_POST$")>;
    345. 

  345. 

  346. // Vector - Integer
    347. 

  347. // -----------------------------------------------------------------------------
    348. 

  348. 

  349. // Reference for forms in this group
    350. 

  350. //   D form - v8i8, v4i16, v2i32
    351. 

  351. //   Q form - v16i8, v8i16, v4i32
    352. 

  352. //   D form - v1i8, v1i16, v1i32, v1i64
    353. 

  353. //   Q form - v16i8, v8i16, v4i32, v2i64
    354. 

  354. //   D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
    355. 

  355. //   Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
    356. 

  356. 

  357. // Cortex A57 Software Optimization Guide Sec 3.14
    358. 

  358. // Advance for absolute diff accum, pairwise add and accumulate, shift accumulate
    359. 

  359. def A57ReadIVA3 : SchedReadAdvance<3, [A57Write_4cyc_1X_NonMul_Forward, A57Write_5cyc_2X_NonMul_Forward]>;
    360. 

  360. 

  361. // ASIMD absolute diff accum, D-form
    362. 

  362. def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
    363. 

  363. // ASIMD absolute diff accum, Q-form
    364. 

  364. def : InstRW<[A57Write_5cyc_2X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>;
    365. 

  365. // ASIMD absolute diff accum long
    366. 

  366. def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABAL")>;
    367. 

  367. 

  368. // ASIMD arith, reduce, 4H/4S
    369. 

  369. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
    370. 

  370. // ASIMD arith, reduce, 8B/8H
    371. 

  371. def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
    372. 

  372. // ASIMD arith, reduce, 16B
    373. 

  373. def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>;
    374. 

  374. 

  375. // ASIMD max/min, reduce, 4H/4S
    376. 

  376. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
    377. 

  377. // ASIMD max/min, reduce, 8B/8H
    378. 

  378. def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
    379. 

  379. // ASIMD max/min, reduce, 16B
    380. 

  380. def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>;
    381. 

  381. 

  382. // ASIMD multiply, D-form
    383. 

  383. // MUL
    384. 

  384. def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
    385. 

  385. // PMUL, SQDMULH, SQRDMULH
    386. 

  386. def : InstRW<[A57Write_5cyc_1W], (instregex "^(PMUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
    387. 

  387. 

  388. // ASIMD multiply, Q-form
    389. 

  389. // MUL
    390. 

  390. def : InstRW<[A57Write_6cyc_2W_Mul_Forward], (instregex "^MUL(v16i8|v8i16|v4i32)(_indexed)?$")>;
    391. 

  391. // PMUL, SQDMULH, SQRDMULH
    392. 

  392. def : InstRW<[A57Write_6cyc_2W], (instregex "^(PMUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
    393. 

  393. 

  394. // Cortex A57 Software Optimization Guide Sec 3.14
    395. 

  395. def A57ReadIVMA4   : SchedReadAdvance<4 , [A57Write_5cyc_1W_Mul_Forward, A57Write_6cyc_2W_Mul_Forward]>;
    396. 

  396. def A57ReadIVMA3   : SchedReadAdvance<3 , [A57Write_5cyc_1W_Mul_Forward, A57Write_6cyc_2W_Mul_Forward]>;
    397. 

  397. 

  398. // ASIMD multiply accumulate, D-form
    399. 

  399. def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
    400. 

  400. // ASIMD multiply accumulate, Q-form
    401. 

  401. def : InstRW<[A57Write_6cyc_2W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>;
    402. 

  402. 

  403. // ASIMD multiply accumulate long
    404. 

  404. // ASIMD multiply accumulate saturating long
    405. 

  405. def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA4], (instregex "^(S|U)ML[AS]L")>;
    406. 

  406. def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA3], (instregex "^SQDML[AS]L")>;
    407. 

  407. 

  408. // ASIMD multiply long
    409. 

  409. def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^(S|U)MULL")>;
    410. 

  410. def : InstRW<[A57Write_5cyc_1W], (instregex "^SQDMULL")>;
    411. 

  411. def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
    412. 

  412. def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>;
    413. 

  413. 

  414. // ASIMD pairwise add and accumulate
    415. 

  415. // ASIMD shift accumulate
    416. 

  416. def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ADALP")>;
    417. 

  417. def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>;
    418. 

  418. 

  419. // ASIMD shift by immed, complex
    420. 

  420. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>;
    421. 

  421. def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>;
    422. 

  422. 

  423. 

  424. // ASIMD shift by register, basic, Q-form
    425. 

  425. def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
    426. 

  426. 

  427. // ASIMD shift by register, complex, D-form
    428. 

  428. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
    429. 

  429. 

  430. // ASIMD shift by register, complex, Q-form
    431. 

  431. def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
    432. 

  432. 

  433. 

  434. // Vector - Floating Point
    435. 

  435. // -----------------------------------------------------------------------------
    436. 

  436. 

  437. // Reference for forms in this group
    438. 

  438. //   D form - v2f32
    439. 

  439. //   Q form - v4f32, v2f64
    440. 

  440. //   D form - 32, 64
    441. 

  441. //   D form - v1i32, v1i64
    442. 

  442. //   D form - v2i32
    443. 

  443. //   Q form - v4i32, v2i64
    444. 

  444. 

  445. // ASIMD FP arith, normal, D-form
    446. 

  446. def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
    447. 

  447. // ASIMD FP arith, normal, Q-form
    448. 

  448. def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
    449. 

  449. 

  450. // ASIMD FP arith, pairwise, D-form
    451. 

  451. def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
    452. 

  452. // ASIMD FP arith, pairwise, Q-form
    453. 

  453. def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
    454. 

  454. 

  455. // ASIMD FP compare, D-form
    456. 

  456. def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
    457. 

  457. // ASIMD FP compare, Q-form
    458. 

  458. def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>;
    459. 

  459. 

  460. // ASIMD FP convert, long and narrow
    461. 

  461. def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>;
    462. 

  462. // ASIMD FP convert, other, D-form
    463. 

  463. def : InstRW<[A57Write_5cyc_1V], (instregex "^[FSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
    464. 

  464. // ASIMD FP convert, other, Q-form
    465. 

  465. def : InstRW<[A57Write_5cyc_2V], (instregex "^[FSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;
    466. 

  466. 

  467. // ASIMD FP divide, D-form, F32
    468. 

  468. def : InstRW<[A57Write_17cyc_1W], (instregex "FDIVv2f32")>;
    469. 

  469. // ASIMD FP divide, Q-form, F32
    470. 

  470. def : InstRW<[A57Write_34cyc_2W], (instregex "FDIVv4f32")>;
    471. 

  471. // ASIMD FP divide, Q-form, F64
    472. 

  472. def : InstRW<[A57Write_64cyc_2W], (instregex "FDIVv2f64")>;
    473. 

  473. 

  474. // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
    475. 

  475. // ASIMD FP square root, D-form, F32
    476. 

  476. def : InstRW<[A57Write_17cyc_1W], (instregex "FSQRTv2f32")>;
    477. 

  477. // ASIMD FP square root, Q-form, F32
    478. 

  478. def : InstRW<[A57Write_34cyc_2W], (instregex "FSQRTv4f32")>;
    479. 

  479. // ASIMD FP square root, Q-form, F64
    480. 

  480. def : InstRW<[A57Write_64cyc_2W], (instregex "FSQRTv2f64")>;
    481. 

  481. 

  482. // ASIMD FP max/min, normal, D-form
    483. 

  483. def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
    484. 

  484. // ASIMD FP max/min, normal, Q-form
    485. 

  485. def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
    486. 

  486. // ASIMD FP max/min, pairwise, D-form
    487. 

  487. def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
    488. 

  488. // ASIMD FP max/min, pairwise, Q-form
    489. 

  489. def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
    490. 

  490. // ASIMD FP max/min, reduce
    491. 

  491. def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
    492. 

  492. 

  493. // ASIMD FP multiply, D-form, FZ
    494. 

  494. def : InstRW<[A57Write_5cyc_1V_FP_Forward], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
    495. 

  495. // ASIMD FP multiply, Q-form, FZ
    496. 

  496. def : InstRW<[A57Write_5cyc_2V_FP_Forward], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
    497. 

  497. 

  498. // ASIMD FP multiply accumulate, D-form, FZ
    499. 

  499. // ASIMD FP multiply accumulate, Q-form, FZ
    500. 

  500. def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
    501. 

  501. def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10;  }
    502. 

  502. 

  503. // Cortex A57 Software Optimization Guide Sec 3.15
    504. 

  504. // Advances from FP mul and mul-accum to mul-accum
    505. 

  505. def A57ReadFPVMA5  : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ, A57Write_5cyc_1V_FP_Forward, A57Write_5cyc_2V_FP_Forward]>;
    506. 

  506. def A57ReadFPVMA6  : SchedReadAdvance<6, [A57WriteFPVMAD, A57WriteFPVMAQ, A57Write_5cyc_1V_FP_Forward, A57Write_5cyc_2V_FP_Forward]>;
    507. 

  507. 

  508. def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
    509. 

  509. def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA6], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
    510. 

  510. 

  511. // ASIMD FP round, D-form
    512. 

  512. def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
    513. 

  513. // ASIMD FP round, Q-form
    514. 

  514. def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
    515. 

  515. 

  516. 

  517. // Vector - Miscellaneous
    518. 

  518. // -----------------------------------------------------------------------------
    519. 

  519. 

  520. // Reference for forms in this group
    521. 

  521. //   D form - v8i8, v4i16, v2i32
    522. 

  522. //   Q form - v16i8, v8i16, v4i32
    523. 

  523. //   D form - v1i8, v1i16, v1i32, v1i64
    524. 

  524. //   Q form - v16i8, v8i16, v4i32, v2i64
    525. 

  525. 

  526. // ASIMD bitwise insert, Q-form
    527. 

  527. def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL|BSP)v16i8")>;
    528. 

  528. 

  529. // ASIMD duplicate, gen reg, D-form and Q-form
    530. 

  530. def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUP(i8|i16|i32|i64)$")>;
    531. 

  531. def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>;
    532. 

  532. 

  533. // ASIMD move, saturating
    534. 

  534. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>;
    535. 

  535. 

  536. // ASIMD reciprocal estimate, D-form
    537. 

  537. def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
    538. 

  538. // ASIMD reciprocal estimate, Q-form
    539. 

  539. def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>;
    540. 

  540. 

  541. // ASIMD reciprocal step, D-form, FZ
    542. 

  542. def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>;
    543. 

  543. // ASIMD reciprocal step, Q-form, FZ
    544. 

  544. def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>;
    545. 

  545. 

  546. // ASIMD table lookup, D-form
    547. 

  547. def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>;
    548. 

  548. def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>;
    549. 

  549. def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>;
    550. 

  550. def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>;
    551. 

  551. // ASIMD table lookup, Q-form
    552. 

  552. def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>;
    553. 

  553. def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>;
    554. 

  554. def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>;
    555. 

  555. def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>;
    556. 

  556. 

  557. // ASIMD transfer, element to gen reg
    558. 

  558. def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>;
    559. 

  559. 

  560. // ASIMD transfer, gen reg to element
    561. 

  561. def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>;
    562. 

  562. 

  563. // ASIMD unzip/zip, Q-form
    564. 

  564. def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>;
    565. 

  565. 

  566. 

  567. // Remainder
    568. 

  568. // -----------------------------------------------------------------------------
    569. 

  569. 

  570. def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>;
    571. 

  571. 

  572. // Cortex A57 Software Optimization Guide Sec 3.10
    573. 

  573. def A57WriteFPMA  : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
    574. 

  574. def A57ReadFPMA5  : SchedReadAdvance<5, [A57WriteFPMA, WriteFMul]>;
    575. 

  575. def A57ReadFPM    : SchedReadAdvance<0>;
    576. 

  576. def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
    577. 

  577. 

  578. def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
    579. 

  579. def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>;
    580. 

  580. 

  581. def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>;
    582. 

  582. def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>;
    583. 

  583. 

  584. def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>;
    585. 

  585. 

  586. def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
    587. 

  587. 

  588. def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>;
    589. 

  589. def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>;
    590. 

  590. 

  591. def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>;
    592. 

  592. def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>;
    593. 

  593. def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>;
    594. 

  594. def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>;
    595. 

  595. def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>;
    596. 

  596. def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>;
    597. 

  597. def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>;
    598. 

  598. def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>;
    599. 

  599. def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>;
    600. 

  600. def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>;
    601. 

  601. def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>;
    602. 

  602. def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>;
    603. 

  603. def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>;
    604. 

  604. def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>;
    605. 

  605. def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>;
    606. 

  606. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
    607. 

  607. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>;
    608. 

  608. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>;
    609. 

  609. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>;
    610. 

  610. def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>;
    611. 

  611. def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>;
    612. 

  612. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
    613. 

  613. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>;
    614. 

  614. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>;
    615. 

  615. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>;
    616. 

  616. def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>;
    617. 

  617. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>;
    618. 

  618. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>;
    619. 

  619. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
    620. 

  620. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>;
    621. 

  621. def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>;
    622. 

  622. def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>;
    623. 

  623. def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>;
    624. 

  624. def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>;
    625. 

  625. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
    626. 

  626. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>;
    627. 

  627. def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>;
    628. 

  628. def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>;
    629. 

  629. def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>;
    630. 

  630. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>;
    631. 

  631. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>;
    632. 

  632. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>;
    633. 

  633. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>;
    634. 

  634. def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>;
    635. 

  635. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
    636. 

  636. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>;
    637. 

  637. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>;
    638. 

  638. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>;
    639. 

  639. def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>;
    640. 

  640. def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>;
    641. 

  641. def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>;
    642. 

  642. def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>;
    643. 

  643. def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>;
    644. 

  644. def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>;
    645. 

  645. 

  646. def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>;
    647. 

  647. def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>;
    648. 

  648. def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>;
    649. 

  649. def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>;
    650. 

  650. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>;
    651. 

  651. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>;
    652. 

  652. def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>;
    653. 

  653. def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>;
    654. 

  654. def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>;
    655. 

  655. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>;
    656. 

  656. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>;
    657. 

  657. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>;
    658. 

  658. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>;
    659. 

  659. def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>;
    660. 

  660. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>;
    661. 

  661. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>;
    662. 

  662. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>;
    663. 

  663. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>;
    664. 

  664. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>;
    665. 

  665. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>;
    666. 

  666. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>;
    667. 

  667. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>;
    668. 

  668. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>;
    669. 

  669. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>;
    670. 

  670. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>;
    671. 

  671. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>;
    672. 

  672. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>;
    673. 

  673. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>;
    674. 

  674. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>;
    675. 

  675. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>;
    676. 

  676. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>;
    677. 

  677. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>;
    678. 

  678. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>;
    679. 

  679. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>;
    680. 

  680. def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>;
    681. 

  681. def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>;
    682. 

  682. def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>;
    683. 

  683. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>;
    684. 

  684. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>;
    685. 

  685. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>;
    686. 

  686. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>;
    687. 

  687. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>;
    688. 

  688. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>;
    689. 

  689. def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>;
    690. 

  690. 

  691. } // SchedModel = CortexA57Model
    692.