jidctint-avx2.asm 17 KB

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  1. ;
  2. ; jidctint.asm - accurate integer IDCT (64-bit AVX2)
  3. ;
  4. ; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
  5. ; Copyright (C) 2009, 2016, 2018, 2020, D. R. Commander.
  6. ; Copyright (C) 2018, Matthias Räncker.
  7. ;
  8. ; Based on the x86 SIMD extension for IJG JPEG library
  9. ; Copyright (C) 1999-2006, MIYASAKA Masaru.
  10. ; For conditions of distribution and use, see copyright notice in jsimdext.inc
  11. ;
  12. ; This file should be assembled with NASM (Netwide Assembler),
  13. ; can *not* be assembled with Microsoft's MASM or any compatible
  14. ; assembler (including Borland's Turbo Assembler).
  15. ; NASM is available from http://nasm.sourceforge.net/ or
  16. ; http://sourceforge.net/project/showfiles.php?group_id=6208
  17. ;
  18. ; This file contains a slower but more accurate integer implementation of the
  19. ; inverse DCT (Discrete Cosine Transform). The following code is based
  20. ; directly on the IJG's original jidctint.c; see the jidctint.c for
  21. ; more details.
  22. %include "jsimdext.inc"
  23. %include "jdct.inc"
  24. ; --------------------------------------------------------------------------
  25. %define CONST_BITS 13
  26. %define PASS1_BITS 2
  27. %define DESCALE_P1 (CONST_BITS - PASS1_BITS)
  28. %define DESCALE_P2 (CONST_BITS + PASS1_BITS + 3)
  29. %if CONST_BITS == 13
  30. F_0_298 equ 2446 ; FIX(0.298631336)
  31. F_0_390 equ 3196 ; FIX(0.390180644)
  32. F_0_541 equ 4433 ; FIX(0.541196100)
  33. F_0_765 equ 6270 ; FIX(0.765366865)
  34. F_0_899 equ 7373 ; FIX(0.899976223)
  35. F_1_175 equ 9633 ; FIX(1.175875602)
  36. F_1_501 equ 12299 ; FIX(1.501321110)
  37. F_1_847 equ 15137 ; FIX(1.847759065)
  38. F_1_961 equ 16069 ; FIX(1.961570560)
  39. F_2_053 equ 16819 ; FIX(2.053119869)
  40. F_2_562 equ 20995 ; FIX(2.562915447)
  41. F_3_072 equ 25172 ; FIX(3.072711026)
  42. %else
  43. ; NASM cannot do compile-time arithmetic on floating-point constants.
  44. %define DESCALE(x, n) (((x) + (1 << ((n) - 1))) >> (n))
  45. F_0_298 equ DESCALE( 320652955, 30 - CONST_BITS) ; FIX(0.298631336)
  46. F_0_390 equ DESCALE( 418953276, 30 - CONST_BITS) ; FIX(0.390180644)
  47. F_0_541 equ DESCALE( 581104887, 30 - CONST_BITS) ; FIX(0.541196100)
  48. F_0_765 equ DESCALE( 821806413, 30 - CONST_BITS) ; FIX(0.765366865)
  49. F_0_899 equ DESCALE( 966342111, 30 - CONST_BITS) ; FIX(0.899976223)
  50. F_1_175 equ DESCALE(1262586813, 30 - CONST_BITS) ; FIX(1.175875602)
  51. F_1_501 equ DESCALE(1612031267, 30 - CONST_BITS) ; FIX(1.501321110)
  52. F_1_847 equ DESCALE(1984016188, 30 - CONST_BITS) ; FIX(1.847759065)
  53. F_1_961 equ DESCALE(2106220350, 30 - CONST_BITS) ; FIX(1.961570560)
  54. F_2_053 equ DESCALE(2204520673, 30 - CONST_BITS) ; FIX(2.053119869)
  55. F_2_562 equ DESCALE(2751909506, 30 - CONST_BITS) ; FIX(2.562915447)
  56. F_3_072 equ DESCALE(3299298341, 30 - CONST_BITS) ; FIX(3.072711026)
  57. %endif
  58. ; --------------------------------------------------------------------------
  59. ; In-place 8x8x16-bit inverse matrix transpose using AVX2 instructions
  60. ; %1-%4: Input/output registers
  61. ; %5-%8: Temp registers
  62. %macro dotranspose 8
  63. ; %5=(00 10 20 30 40 50 60 70 01 11 21 31 41 51 61 71)
  64. ; %6=(03 13 23 33 43 53 63 73 02 12 22 32 42 52 62 72)
  65. ; %7=(04 14 24 34 44 54 64 74 05 15 25 35 45 55 65 75)
  66. ; %8=(07 17 27 37 47 57 67 77 06 16 26 36 46 56 66 76)
  67. vpermq %5, %1, 0xD8
  68. vpermq %6, %2, 0x72
  69. vpermq %7, %3, 0xD8
  70. vpermq %8, %4, 0x72
  71. ; transpose coefficients(phase 1)
  72. ; %5=(00 10 20 30 01 11 21 31 40 50 60 70 41 51 61 71)
  73. ; %6=(02 12 22 32 03 13 23 33 42 52 62 72 43 53 63 73)
  74. ; %7=(04 14 24 34 05 15 25 35 44 54 64 74 45 55 65 75)
  75. ; %8=(06 16 26 36 07 17 27 37 46 56 66 76 47 57 67 77)
  76. vpunpcklwd %1, %5, %6
  77. vpunpckhwd %2, %5, %6
  78. vpunpcklwd %3, %7, %8
  79. vpunpckhwd %4, %7, %8
  80. ; transpose coefficients(phase 2)
  81. ; %1=(00 02 10 12 20 22 30 32 40 42 50 52 60 62 70 72)
  82. ; %2=(01 03 11 13 21 23 31 33 41 43 51 53 61 63 71 73)
  83. ; %3=(04 06 14 16 24 26 34 36 44 46 54 56 64 66 74 76)
  84. ; %4=(05 07 15 17 25 27 35 37 45 47 55 57 65 67 75 77)
  85. vpunpcklwd %5, %1, %2
  86. vpunpcklwd %6, %3, %4
  87. vpunpckhwd %7, %1, %2
  88. vpunpckhwd %8, %3, %4
  89. ; transpose coefficients(phase 3)
  90. ; %5=(00 01 02 03 10 11 12 13 40 41 42 43 50 51 52 53)
  91. ; %6=(04 05 06 07 14 15 16 17 44 45 46 47 54 55 56 57)
  92. ; %7=(20 21 22 23 30 31 32 33 60 61 62 63 70 71 72 73)
  93. ; %8=(24 25 26 27 34 35 36 37 64 65 66 67 74 75 76 77)
  94. vpunpcklqdq %1, %5, %6
  95. vpunpckhqdq %2, %5, %6
  96. vpunpcklqdq %3, %7, %8
  97. vpunpckhqdq %4, %7, %8
  98. ; transpose coefficients(phase 4)
  99. ; %1=(00 01 02 03 04 05 06 07 40 41 42 43 44 45 46 47)
  100. ; %2=(10 11 12 13 14 15 16 17 50 51 52 53 54 55 56 57)
  101. ; %3=(20 21 22 23 24 25 26 27 60 61 62 63 64 65 66 67)
  102. ; %4=(30 31 32 33 34 35 36 37 70 71 72 73 74 75 76 77)
  103. %endmacro
  104. ; --------------------------------------------------------------------------
  105. ; In-place 8x8x16-bit accurate integer inverse DCT using AVX2 instructions
  106. ; %1-%4: Input/output registers
  107. ; %5-%12: Temp registers
  108. ; %9: Pass (1 or 2)
  109. %macro dodct 13
  110. ; -- Even part
  111. ; (Original)
  112. ; z1 = (z2 + z3) * 0.541196100;
  113. ; tmp2 = z1 + z3 * -1.847759065;
  114. ; tmp3 = z1 + z2 * 0.765366865;
  115. ;
  116. ; (This implementation)
  117. ; tmp2 = z2 * 0.541196100 + z3 * (0.541196100 - 1.847759065);
  118. ; tmp3 = z2 * (0.541196100 + 0.765366865) + z3 * 0.541196100;
  119. vperm2i128 %6, %3, %3, 0x01 ; %6=in6_2
  120. vpunpcklwd %5, %3, %6 ; %5=in26_62L
  121. vpunpckhwd %6, %3, %6 ; %6=in26_62H
  122. vpmaddwd %5, %5, [rel PW_F130_F054_MF130_F054] ; %5=tmp3_2L
  123. vpmaddwd %6, %6, [rel PW_F130_F054_MF130_F054] ; %6=tmp3_2H
  124. vperm2i128 %7, %1, %1, 0x01 ; %7=in4_0
  125. vpsignw %1, %1, [rel PW_1_NEG1]
  126. vpaddw %7, %7, %1 ; %7=(in0+in4)_(in0-in4)
  127. vpxor %1, %1, %1
  128. vpunpcklwd %8, %1, %7 ; %8=tmp0_1L
  129. vpunpckhwd %1, %1, %7 ; %1=tmp0_1H
  130. vpsrad %8, %8, (16-CONST_BITS) ; vpsrad %8,16 & vpslld %8,CONST_BITS
  131. vpsrad %1, %1, (16-CONST_BITS) ; vpsrad %1,16 & vpslld %1,CONST_BITS
  132. vpsubd %11, %8, %5 ; %11=tmp0_1L-tmp3_2L=tmp13_12L
  133. vpaddd %9, %8, %5 ; %9=tmp0_1L+tmp3_2L=tmp10_11L
  134. vpsubd %12, %1, %6 ; %12=tmp0_1H-tmp3_2H=tmp13_12H
  135. vpaddd %10, %1, %6 ; %10=tmp0_1H+tmp3_2H=tmp10_11H
  136. ; -- Odd part
  137. vpaddw %1, %4, %2 ; %1=in7_5+in3_1=z3_4
  138. ; (Original)
  139. ; z5 = (z3 + z4) * 1.175875602;
  140. ; z3 = z3 * -1.961570560; z4 = z4 * -0.390180644;
  141. ; z3 += z5; z4 += z5;
  142. ;
  143. ; (This implementation)
  144. ; z3 = z3 * (1.175875602 - 1.961570560) + z4 * 1.175875602;
  145. ; z4 = z3 * 1.175875602 + z4 * (1.175875602 - 0.390180644);
  146. vperm2i128 %8, %1, %1, 0x01 ; %8=z4_3
  147. vpunpcklwd %7, %1, %8 ; %7=z34_43L
  148. vpunpckhwd %8, %1, %8 ; %8=z34_43H
  149. vpmaddwd %7, %7, [rel PW_MF078_F117_F078_F117] ; %7=z3_4L
  150. vpmaddwd %8, %8, [rel PW_MF078_F117_F078_F117] ; %8=z3_4H
  151. ; (Original)
  152. ; z1 = tmp0 + tmp3; z2 = tmp1 + tmp2;
  153. ; tmp0 = tmp0 * 0.298631336; tmp1 = tmp1 * 2.053119869;
  154. ; tmp2 = tmp2 * 3.072711026; tmp3 = tmp3 * 1.501321110;
  155. ; z1 = z1 * -0.899976223; z2 = z2 * -2.562915447;
  156. ; tmp0 += z1 + z3; tmp1 += z2 + z4;
  157. ; tmp2 += z2 + z3; tmp3 += z1 + z4;
  158. ;
  159. ; (This implementation)
  160. ; tmp0 = tmp0 * (0.298631336 - 0.899976223) + tmp3 * -0.899976223;
  161. ; tmp1 = tmp1 * (2.053119869 - 2.562915447) + tmp2 * -2.562915447;
  162. ; tmp2 = tmp1 * -2.562915447 + tmp2 * (3.072711026 - 2.562915447);
  163. ; tmp3 = tmp0 * -0.899976223 + tmp3 * (1.501321110 - 0.899976223);
  164. ; tmp0 += z3; tmp1 += z4;
  165. ; tmp2 += z3; tmp3 += z4;
  166. vperm2i128 %2, %2, %2, 0x01 ; %2=in1_3
  167. vpunpcklwd %3, %4, %2 ; %3=in71_53L
  168. vpunpckhwd %4, %4, %2 ; %4=in71_53H
  169. vpmaddwd %5, %3, [rel PW_MF060_MF089_MF050_MF256] ; %5=tmp0_1L
  170. vpmaddwd %6, %4, [rel PW_MF060_MF089_MF050_MF256] ; %6=tmp0_1H
  171. vpaddd %5, %5, %7 ; %5=tmp0_1L+z3_4L=tmp0_1L
  172. vpaddd %6, %6, %8 ; %6=tmp0_1H+z3_4H=tmp0_1H
  173. vpmaddwd %3, %3, [rel PW_MF089_F060_MF256_F050] ; %3=tmp3_2L
  174. vpmaddwd %4, %4, [rel PW_MF089_F060_MF256_F050] ; %4=tmp3_2H
  175. vperm2i128 %7, %7, %7, 0x01 ; %7=z4_3L
  176. vperm2i128 %8, %8, %8, 0x01 ; %8=z4_3H
  177. vpaddd %7, %3, %7 ; %7=tmp3_2L+z4_3L=tmp3_2L
  178. vpaddd %8, %4, %8 ; %8=tmp3_2H+z4_3H=tmp3_2H
  179. ; -- Final output stage
  180. vpaddd %1, %9, %7 ; %1=tmp10_11L+tmp3_2L=data0_1L
  181. vpaddd %2, %10, %8 ; %2=tmp10_11H+tmp3_2H=data0_1H
  182. vpaddd %1, %1, [rel PD_DESCALE_P %+ %13]
  183. vpaddd %2, %2, [rel PD_DESCALE_P %+ %13]
  184. vpsrad %1, %1, DESCALE_P %+ %13
  185. vpsrad %2, %2, DESCALE_P %+ %13
  186. vpackssdw %1, %1, %2 ; %1=data0_1
  187. vpsubd %3, %9, %7 ; %3=tmp10_11L-tmp3_2L=data7_6L
  188. vpsubd %4, %10, %8 ; %4=tmp10_11H-tmp3_2H=data7_6H
  189. vpaddd %3, %3, [rel PD_DESCALE_P %+ %13]
  190. vpaddd %4, %4, [rel PD_DESCALE_P %+ %13]
  191. vpsrad %3, %3, DESCALE_P %+ %13
  192. vpsrad %4, %4, DESCALE_P %+ %13
  193. vpackssdw %4, %3, %4 ; %4=data7_6
  194. vpaddd %7, %11, %5 ; %7=tmp13_12L+tmp0_1L=data3_2L
  195. vpaddd %8, %12, %6 ; %8=tmp13_12H+tmp0_1H=data3_2H
  196. vpaddd %7, %7, [rel PD_DESCALE_P %+ %13]
  197. vpaddd %8, %8, [rel PD_DESCALE_P %+ %13]
  198. vpsrad %7, %7, DESCALE_P %+ %13
  199. vpsrad %8, %8, DESCALE_P %+ %13
  200. vpackssdw %2, %7, %8 ; %2=data3_2
  201. vpsubd %7, %11, %5 ; %7=tmp13_12L-tmp0_1L=data4_5L
  202. vpsubd %8, %12, %6 ; %8=tmp13_12H-tmp0_1H=data4_5H
  203. vpaddd %7, %7, [rel PD_DESCALE_P %+ %13]
  204. vpaddd %8, %8, [rel PD_DESCALE_P %+ %13]
  205. vpsrad %7, %7, DESCALE_P %+ %13
  206. vpsrad %8, %8, DESCALE_P %+ %13
  207. vpackssdw %3, %7, %8 ; %3=data4_5
  208. %endmacro
  209. ; --------------------------------------------------------------------------
  210. SECTION SEG_CONST
  211. alignz 32
  212. GLOBAL_DATA(jconst_idct_islow_avx2)
  213. EXTN(jconst_idct_islow_avx2):
  214. PW_F130_F054_MF130_F054 times 4 dw (F_0_541 + F_0_765), F_0_541
  215. times 4 dw (F_0_541 - F_1_847), F_0_541
  216. PW_MF078_F117_F078_F117 times 4 dw (F_1_175 - F_1_961), F_1_175
  217. times 4 dw (F_1_175 - F_0_390), F_1_175
  218. PW_MF060_MF089_MF050_MF256 times 4 dw (F_0_298 - F_0_899), -F_0_899
  219. times 4 dw (F_2_053 - F_2_562), -F_2_562
  220. PW_MF089_F060_MF256_F050 times 4 dw -F_0_899, (F_1_501 - F_0_899)
  221. times 4 dw -F_2_562, (F_3_072 - F_2_562)
  222. PD_DESCALE_P1 times 8 dd 1 << (DESCALE_P1 - 1)
  223. PD_DESCALE_P2 times 8 dd 1 << (DESCALE_P2 - 1)
  224. PB_CENTERJSAMP times 32 db CENTERJSAMPLE
  225. PW_1_NEG1 times 8 dw 1
  226. times 8 dw -1
  227. alignz 32
  228. ; --------------------------------------------------------------------------
  229. SECTION SEG_TEXT
  230. BITS 64
  231. ;
  232. ; Perform dequantization and inverse DCT on one block of coefficients.
  233. ;
  234. ; GLOBAL(void)
  235. ; jsimd_idct_islow_avx2(void *dct_table, JCOEFPTR coef_block,
  236. ; JSAMPARRAY output_buf, JDIMENSION output_col)
  237. ;
  238. ; r10 = jpeg_component_info *compptr
  239. ; r11 = JCOEFPTR coef_block
  240. ; r12 = JSAMPARRAY output_buf
  241. ; r13d = JDIMENSION output_col
  242. align 32
  243. GLOBAL_FUNCTION(jsimd_idct_islow_avx2)
  244. EXTN(jsimd_idct_islow_avx2):
  245. push rbp
  246. mov rax, rsp ; rax = original rbp
  247. mov rbp, rsp ; rbp = aligned rbp
  248. push_xmm 4
  249. collect_args 4
  250. ; ---- Pass 1: process columns.
  251. %ifndef NO_ZERO_COLUMN_TEST_ISLOW_AVX2
  252. mov eax, dword [DWBLOCK(1,0,r11,SIZEOF_JCOEF)]
  253. or eax, dword [DWBLOCK(2,0,r11,SIZEOF_JCOEF)]
  254. jnz near .columnDCT
  255. movdqa xmm0, XMMWORD [XMMBLOCK(1,0,r11,SIZEOF_JCOEF)]
  256. movdqa xmm1, XMMWORD [XMMBLOCK(2,0,r11,SIZEOF_JCOEF)]
  257. vpor xmm0, xmm0, XMMWORD [XMMBLOCK(3,0,r11,SIZEOF_JCOEF)]
  258. vpor xmm1, xmm1, XMMWORD [XMMBLOCK(4,0,r11,SIZEOF_JCOEF)]
  259. vpor xmm0, xmm0, XMMWORD [XMMBLOCK(5,0,r11,SIZEOF_JCOEF)]
  260. vpor xmm1, xmm1, XMMWORD [XMMBLOCK(6,0,r11,SIZEOF_JCOEF)]
  261. vpor xmm0, xmm0, XMMWORD [XMMBLOCK(7,0,r11,SIZEOF_JCOEF)]
  262. vpor xmm1, xmm1, xmm0
  263. vpacksswb xmm1, xmm1, xmm1
  264. vpacksswb xmm1, xmm1, xmm1
  265. movd eax, xmm1
  266. test rax, rax
  267. jnz short .columnDCT
  268. ; -- AC terms all zero
  269. movdqa xmm5, XMMWORD [XMMBLOCK(0,0,r11,SIZEOF_JCOEF)]
  270. vpmullw xmm5, xmm5, XMMWORD [XMMBLOCK(0,0,r10,SIZEOF_ISLOW_MULT_TYPE)]
  271. vpsllw xmm5, xmm5, PASS1_BITS
  272. vpunpcklwd xmm4, xmm5, xmm5 ; xmm4=(00 00 01 01 02 02 03 03)
  273. vpunpckhwd xmm5, xmm5, xmm5 ; xmm5=(04 04 05 05 06 06 07 07)
  274. vinserti128 ymm4, ymm4, xmm5, 1
  275. vpshufd ymm0, ymm4, 0x00 ; ymm0=col0_4=(00 00 00 00 00 00 00 00 04 04 04 04 04 04 04 04)
  276. vpshufd ymm1, ymm4, 0x55 ; ymm1=col1_5=(01 01 01 01 01 01 01 01 05 05 05 05 05 05 05 05)
  277. vpshufd ymm2, ymm4, 0xAA ; ymm2=col2_6=(02 02 02 02 02 02 02 02 06 06 06 06 06 06 06 06)
  278. vpshufd ymm3, ymm4, 0xFF ; ymm3=col3_7=(03 03 03 03 03 03 03 03 07 07 07 07 07 07 07 07)
  279. jmp near .column_end
  280. %endif
  281. .columnDCT:
  282. vmovdqu ymm4, YMMWORD [YMMBLOCK(0,0,r11,SIZEOF_JCOEF)] ; ymm4=in0_1
  283. vmovdqu ymm5, YMMWORD [YMMBLOCK(2,0,r11,SIZEOF_JCOEF)] ; ymm5=in2_3
  284. vmovdqu ymm6, YMMWORD [YMMBLOCK(4,0,r11,SIZEOF_JCOEF)] ; ymm6=in4_5
  285. vmovdqu ymm7, YMMWORD [YMMBLOCK(6,0,r11,SIZEOF_JCOEF)] ; ymm7=in6_7
  286. vpmullw ymm4, ymm4, YMMWORD [YMMBLOCK(0,0,r10,SIZEOF_ISLOW_MULT_TYPE)]
  287. vpmullw ymm5, ymm5, YMMWORD [YMMBLOCK(2,0,r10,SIZEOF_ISLOW_MULT_TYPE)]
  288. vpmullw ymm6, ymm6, YMMWORD [YMMBLOCK(4,0,r10,SIZEOF_ISLOW_MULT_TYPE)]
  289. vpmullw ymm7, ymm7, YMMWORD [YMMBLOCK(6,0,r10,SIZEOF_ISLOW_MULT_TYPE)]
  290. vperm2i128 ymm0, ymm4, ymm6, 0x20 ; ymm0=in0_4
  291. vperm2i128 ymm1, ymm5, ymm4, 0x31 ; ymm1=in3_1
  292. vperm2i128 ymm2, ymm5, ymm7, 0x20 ; ymm2=in2_6
  293. vperm2i128 ymm3, ymm7, ymm6, 0x31 ; ymm3=in7_5
  294. dodct ymm0, ymm1, ymm2, ymm3, ymm4, ymm5, ymm6, ymm7, ymm8, ymm9, ymm10, ymm11, 1
  295. ; ymm0=data0_1, ymm1=data3_2, ymm2=data4_5, ymm3=data7_6
  296. dotranspose ymm0, ymm1, ymm2, ymm3, ymm4, ymm5, ymm6, ymm7
  297. ; ymm0=data0_4, ymm1=data1_5, ymm2=data2_6, ymm3=data3_7
  298. .column_end:
  299. ; -- Prefetch the next coefficient block
  300. prefetchnta [r11 + DCTSIZE2*SIZEOF_JCOEF + 0*32]
  301. prefetchnta [r11 + DCTSIZE2*SIZEOF_JCOEF + 1*32]
  302. prefetchnta [r11 + DCTSIZE2*SIZEOF_JCOEF + 2*32]
  303. prefetchnta [r11 + DCTSIZE2*SIZEOF_JCOEF + 3*32]
  304. ; ---- Pass 2: process rows.
  305. vperm2i128 ymm4, ymm3, ymm1, 0x31 ; ymm3=in7_5
  306. vperm2i128 ymm1, ymm3, ymm1, 0x20 ; ymm1=in3_1
  307. dodct ymm0, ymm1, ymm2, ymm4, ymm3, ymm5, ymm6, ymm7, ymm8, ymm9, ymm10, ymm11, 2
  308. ; ymm0=data0_1, ymm1=data3_2, ymm2=data4_5, ymm4=data7_6
  309. dotranspose ymm0, ymm1, ymm2, ymm4, ymm3, ymm5, ymm6, ymm7
  310. ; ymm0=data0_4, ymm1=data1_5, ymm2=data2_6, ymm4=data3_7
  311. vpacksswb ymm0, ymm0, ymm1 ; ymm0=data01_45
  312. vpacksswb ymm1, ymm2, ymm4 ; ymm1=data23_67
  313. vpaddb ymm0, ymm0, [rel PB_CENTERJSAMP]
  314. vpaddb ymm1, ymm1, [rel PB_CENTERJSAMP]
  315. vextracti128 xmm6, ymm1, 1 ; xmm3=data67
  316. vextracti128 xmm4, ymm0, 1 ; xmm2=data45
  317. vextracti128 xmm2, ymm1, 0 ; xmm1=data23
  318. vextracti128 xmm0, ymm0, 0 ; xmm0=data01
  319. vpshufd xmm1, xmm0, 0x4E ; xmm1=(10 11 12 13 14 15 16 17 00 01 02 03 04 05 06 07)
  320. vpshufd xmm3, xmm2, 0x4E ; xmm3=(30 31 32 33 34 35 36 37 20 21 22 23 24 25 26 27)
  321. vpshufd xmm5, xmm4, 0x4E ; xmm5=(50 51 52 53 54 55 56 57 40 41 42 43 44 45 46 47)
  322. vpshufd xmm7, xmm6, 0x4E ; xmm7=(70 71 72 73 74 75 76 77 60 61 62 63 64 65 66 67)
  323. vzeroupper
  324. mov eax, r13d
  325. mov rdxp, JSAMPROW [r12+0*SIZEOF_JSAMPROW] ; (JSAMPLE *)
  326. mov rsip, JSAMPROW [r12+1*SIZEOF_JSAMPROW] ; (JSAMPLE *)
  327. movq XMM_MMWORD [rdx+rax*SIZEOF_JSAMPLE], xmm0
  328. movq XMM_MMWORD [rsi+rax*SIZEOF_JSAMPLE], xmm1
  329. mov rdxp, JSAMPROW [r12+2*SIZEOF_JSAMPROW] ; (JSAMPLE *)
  330. mov rsip, JSAMPROW [r12+3*SIZEOF_JSAMPROW] ; (JSAMPLE *)
  331. movq XMM_MMWORD [rdx+rax*SIZEOF_JSAMPLE], xmm2
  332. movq XMM_MMWORD [rsi+rax*SIZEOF_JSAMPLE], xmm3
  333. mov rdxp, JSAMPROW [r12+4*SIZEOF_JSAMPROW] ; (JSAMPLE *)
  334. mov rsip, JSAMPROW [r12+5*SIZEOF_JSAMPROW] ; (JSAMPLE *)
  335. movq XMM_MMWORD [rdx+rax*SIZEOF_JSAMPLE], xmm4
  336. movq XMM_MMWORD [rsi+rax*SIZEOF_JSAMPLE], xmm5
  337. mov rdxp, JSAMPROW [r12+6*SIZEOF_JSAMPROW] ; (JSAMPLE *)
  338. mov rsip, JSAMPROW [r12+7*SIZEOF_JSAMPROW] ; (JSAMPLE *)
  339. movq XMM_MMWORD [rdx+rax*SIZEOF_JSAMPLE], xmm6
  340. movq XMM_MMWORD [rsi+rax*SIZEOF_JSAMPLE], xmm7
  341. uncollect_args 4
  342. pop_xmm 4
  343. pop rbp
  344. ret
  345. ; For some reason, the OS X linker does not honor the request to align the
  346. ; segment unless we do this.
  347. align 32