DwarfExpression.cpp 25 KB

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  1. //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //===----------------------------------------------------------------------===//
  8. //
  9. // This file contains support for writing dwarf debug info into asm files.
  10. //
  11. //===----------------------------------------------------------------------===//
  12. #include "DwarfExpression.h"
  13. #include "DwarfCompileUnit.h"
  14. #include "llvm/ADT/APInt.h"
  15. #include "llvm/ADT/SmallBitVector.h"
  16. #include "llvm/BinaryFormat/Dwarf.h"
  17. #include "llvm/CodeGen/Register.h"
  18. #include "llvm/CodeGen/TargetRegisterInfo.h"
  19. #include "llvm/IR/DataLayout.h"
  20. #include "llvm/Support/ErrorHandling.h"
  21. #include <algorithm>
  22. using namespace llvm;
  23. #define DEBUG_TYPE "dwarfdebug"
  24. void DwarfExpression::emitConstu(uint64_t Value) {
  25. if (Value < 32)
  26. emitOp(dwarf::DW_OP_lit0 + Value);
  27. else if (Value == std::numeric_limits<uint64_t>::max()) {
  28. // Only do this for 64-bit values as the DWARF expression stack uses
  29. // target-address-size values.
  30. emitOp(dwarf::DW_OP_lit0);
  31. emitOp(dwarf::DW_OP_not);
  32. } else {
  33. emitOp(dwarf::DW_OP_constu);
  34. emitUnsigned(Value);
  35. }
  36. }
  37. void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
  38. assert(DwarfReg >= 0 && "invalid negative dwarf register number");
  39. assert((isUnknownLocation() || isRegisterLocation()) &&
  40. "location description already locked down");
  41. LocationKind = Register;
  42. if (DwarfReg < 32) {
  43. emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
  44. } else {
  45. emitOp(dwarf::DW_OP_regx, Comment);
  46. emitUnsigned(DwarfReg);
  47. }
  48. }
  49. void DwarfExpression::addBReg(int DwarfReg, int Offset) {
  50. assert(DwarfReg >= 0 && "invalid negative dwarf register number");
  51. assert(!isRegisterLocation() && "location description already locked down");
  52. if (DwarfReg < 32) {
  53. emitOp(dwarf::DW_OP_breg0 + DwarfReg);
  54. } else {
  55. emitOp(dwarf::DW_OP_bregx);
  56. emitUnsigned(DwarfReg);
  57. }
  58. emitSigned(Offset);
  59. }
  60. void DwarfExpression::addFBReg(int Offset) {
  61. emitOp(dwarf::DW_OP_fbreg);
  62. emitSigned(Offset);
  63. }
  64. void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
  65. if (!SizeInBits)
  66. return;
  67. const unsigned SizeOfByte = 8;
  68. if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
  69. emitOp(dwarf::DW_OP_bit_piece);
  70. emitUnsigned(SizeInBits);
  71. emitUnsigned(OffsetInBits);
  72. } else {
  73. emitOp(dwarf::DW_OP_piece);
  74. unsigned ByteSize = SizeInBits / SizeOfByte;
  75. emitUnsigned(ByteSize);
  76. }
  77. this->OffsetInBits += SizeInBits;
  78. }
  79. void DwarfExpression::addShr(unsigned ShiftBy) {
  80. emitConstu(ShiftBy);
  81. emitOp(dwarf::DW_OP_shr);
  82. }
  83. void DwarfExpression::addAnd(unsigned Mask) {
  84. emitConstu(Mask);
  85. emitOp(dwarf::DW_OP_and);
  86. }
  87. bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
  88. llvm::Register MachineReg,
  89. unsigned MaxSize) {
  90. if (!MachineReg.isPhysical()) {
  91. if (isFrameRegister(TRI, MachineReg)) {
  92. DwarfRegs.push_back(Register::createRegister(-1, nullptr));
  93. return true;
  94. }
  95. return false;
  96. }
  97. int Reg = TRI.getDwarfRegNum(MachineReg, false);
  98. // If this is a valid register number, emit it.
  99. if (Reg >= 0) {
  100. DwarfRegs.push_back(Register::createRegister(Reg, nullptr));
  101. return true;
  102. }
  103. // Walk up the super-register chain until we find a valid number.
  104. // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
  105. for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
  106. Reg = TRI.getDwarfRegNum(*SR, false);
  107. if (Reg >= 0) {
  108. unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
  109. unsigned Size = TRI.getSubRegIdxSize(Idx);
  110. unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
  111. DwarfRegs.push_back(Register::createRegister(Reg, "super-register"));
  112. // Use a DW_OP_bit_piece to describe the sub-register.
  113. setSubRegisterPiece(Size, RegOffset);
  114. return true;
  115. }
  116. }
  117. // Otherwise, attempt to find a covering set of sub-register numbers.
  118. // For example, Q0 on ARM is a composition of D0+D1.
  119. unsigned CurPos = 0;
  120. // The size of the register in bits.
  121. const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
  122. unsigned RegSize = TRI.getRegSizeInBits(*RC);
  123. // Keep track of the bits in the register we already emitted, so we
  124. // can avoid emitting redundant aliasing subregs. Because this is
  125. // just doing a greedy scan of all subregisters, it is possible that
  126. // this doesn't find a combination of subregisters that fully cover
  127. // the register (even though one may exist).
  128. SmallBitVector Coverage(RegSize, false);
  129. for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
  130. unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
  131. unsigned Size = TRI.getSubRegIdxSize(Idx);
  132. unsigned Offset = TRI.getSubRegIdxOffset(Idx);
  133. Reg = TRI.getDwarfRegNum(*SR, false);
  134. if (Reg < 0)
  135. continue;
  136. // Used to build the intersection between the bits we already
  137. // emitted and the bits covered by this subregister.
  138. SmallBitVector CurSubReg(RegSize, false);
  139. CurSubReg.set(Offset, Offset + Size);
  140. // If this sub-register has a DWARF number and we haven't covered
  141. // its range, and its range covers the value, emit a DWARF piece for it.
  142. if (Offset < MaxSize && CurSubReg.test(Coverage)) {
  143. // Emit a piece for any gap in the coverage.
  144. if (Offset > CurPos)
  145. DwarfRegs.push_back(Register::createSubRegister(
  146. -1, Offset - CurPos, "no DWARF register encoding"));
  147. if (Offset == 0 && Size >= MaxSize)
  148. DwarfRegs.push_back(Register::createRegister(Reg, "sub-register"));
  149. else
  150. DwarfRegs.push_back(Register::createSubRegister(
  151. Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"));
  152. }
  153. // Mark it as emitted.
  154. Coverage.set(Offset, Offset + Size);
  155. CurPos = Offset + Size;
  156. }
  157. // Failed to find any DWARF encoding.
  158. if (CurPos == 0)
  159. return false;
  160. // Found a partial or complete DWARF encoding.
  161. if (CurPos < RegSize)
  162. DwarfRegs.push_back(Register::createSubRegister(
  163. -1, RegSize - CurPos, "no DWARF register encoding"));
  164. return true;
  165. }
  166. void DwarfExpression::addStackValue() {
  167. if (DwarfVersion >= 4)
  168. emitOp(dwarf::DW_OP_stack_value);
  169. }
  170. void DwarfExpression::addSignedConstant(int64_t Value) {
  171. assert(isImplicitLocation() || isUnknownLocation());
  172. LocationKind = Implicit;
  173. emitOp(dwarf::DW_OP_consts);
  174. emitSigned(Value);
  175. }
  176. void DwarfExpression::addUnsignedConstant(uint64_t Value) {
  177. assert(isImplicitLocation() || isUnknownLocation());
  178. LocationKind = Implicit;
  179. emitConstu(Value);
  180. }
  181. void DwarfExpression::addUnsignedConstant(const APInt &Value) {
  182. assert(isImplicitLocation() || isUnknownLocation());
  183. LocationKind = Implicit;
  184. unsigned Size = Value.getBitWidth();
  185. const uint64_t *Data = Value.getRawData();
  186. // Chop it up into 64-bit pieces, because that's the maximum that
  187. // addUnsignedConstant takes.
  188. unsigned Offset = 0;
  189. while (Offset < Size) {
  190. addUnsignedConstant(*Data++);
  191. if (Offset == 0 && Size <= 64)
  192. break;
  193. addStackValue();
  194. addOpPiece(std::min(Size - Offset, 64u), Offset);
  195. Offset += 64;
  196. }
  197. }
  198. void DwarfExpression::addConstantFP(const APFloat &APF, const AsmPrinter &AP) {
  199. assert(isImplicitLocation() || isUnknownLocation());
  200. APInt API = APF.bitcastToAPInt();
  201. int NumBytes = API.getBitWidth() / 8;
  202. if (NumBytes == 4 /*float*/ || NumBytes == 8 /*double*/) {
  203. // FIXME: Add support for `long double`.
  204. emitOp(dwarf::DW_OP_implicit_value);
  205. emitUnsigned(NumBytes /*Size of the block in bytes*/);
  206. // The loop below is emitting the value starting at least significant byte,
  207. // so we need to perform a byte-swap to get the byte order correct in case
  208. // of a big-endian target.
  209. if (AP.getDataLayout().isBigEndian())
  210. API = API.byteSwap();
  211. for (int i = 0; i < NumBytes; ++i) {
  212. emitData1(API.getZExtValue() & 0xFF);
  213. API = API.lshr(8);
  214. }
  215. return;
  216. }
  217. LLVM_DEBUG(
  218. dbgs() << "Skipped DW_OP_implicit_value creation for ConstantFP of size: "
  219. << API.getBitWidth() << " bits\n");
  220. }
  221. bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
  222. DIExpressionCursor &ExprCursor,
  223. llvm::Register MachineReg,
  224. unsigned FragmentOffsetInBits) {
  225. auto Fragment = ExprCursor.getFragmentInfo();
  226. if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
  227. LocationKind = Unknown;
  228. return false;
  229. }
  230. bool HasComplexExpression = false;
  231. auto Op = ExprCursor.peek();
  232. if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
  233. HasComplexExpression = true;
  234. // If the register can only be described by a complex expression (i.e.,
  235. // multiple subregisters) it doesn't safely compose with another complex
  236. // expression. For example, it is not possible to apply a DW_OP_deref
  237. // operation to multiple DW_OP_pieces, since composite location descriptions
  238. // do not push anything on the DWARF stack.
  239. //
  240. // DW_OP_entry_value operations can only hold a DWARF expression or a
  241. // register location description, so we can't emit a single entry value
  242. // covering a composite location description. In the future we may want to
  243. // emit entry value operations for each register location in the composite
  244. // location, but until that is supported do not emit anything.
  245. if ((HasComplexExpression || IsEmittingEntryValue) && DwarfRegs.size() > 1) {
  246. if (IsEmittingEntryValue)
  247. cancelEntryValue();
  248. DwarfRegs.clear();
  249. LocationKind = Unknown;
  250. return false;
  251. }
  252. // Handle simple register locations. If we are supposed to emit
  253. // a call site parameter expression and if that expression is just a register
  254. // location, emit it with addBReg and offset 0, because we should emit a DWARF
  255. // expression representing a value, rather than a location.
  256. if ((!isParameterValue() && !isMemoryLocation() && !HasComplexExpression) ||
  257. isEntryValue()) {
  258. auto FragmentInfo = ExprCursor.getFragmentInfo();
  259. unsigned RegSize = 0;
  260. for (auto &Reg : DwarfRegs) {
  261. RegSize += Reg.SubRegSize;
  262. if (Reg.DwarfRegNo >= 0)
  263. addReg(Reg.DwarfRegNo, Reg.Comment);
  264. if (FragmentInfo)
  265. if (RegSize > FragmentInfo->SizeInBits)
  266. // If the register is larger than the current fragment stop
  267. // once the fragment is covered.
  268. break;
  269. addOpPiece(Reg.SubRegSize);
  270. }
  271. if (isEntryValue()) {
  272. finalizeEntryValue();
  273. if (!isIndirect() && !isParameterValue() && !HasComplexExpression &&
  274. DwarfVersion >= 4)
  275. emitOp(dwarf::DW_OP_stack_value);
  276. }
  277. DwarfRegs.clear();
  278. // If we need to mask out a subregister, do it now, unless the next
  279. // operation would emit an OpPiece anyway.
  280. auto NextOp = ExprCursor.peek();
  281. if (SubRegisterSizeInBits && NextOp &&
  282. (NextOp->getOp() != dwarf::DW_OP_LLVM_fragment))
  283. maskSubRegister();
  284. return true;
  285. }
  286. // Don't emit locations that cannot be expressed without DW_OP_stack_value.
  287. if (DwarfVersion < 4)
  288. if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
  289. return Op.getOp() == dwarf::DW_OP_stack_value;
  290. })) {
  291. DwarfRegs.clear();
  292. LocationKind = Unknown;
  293. return false;
  294. }
  295. // TODO: We should not give up here but the following code needs to be changed
  296. // to deal with multiple (sub)registers first.
  297. if (DwarfRegs.size() > 1) {
  298. LLVM_DEBUG(dbgs() << "TODO: giving up on debug information due to "
  299. "multi-register usage.\n");
  300. DwarfRegs.clear();
  301. LocationKind = Unknown;
  302. return false;
  303. }
  304. auto Reg = DwarfRegs[0];
  305. bool FBReg = isFrameRegister(TRI, MachineReg);
  306. int SignedOffset = 0;
  307. assert(!Reg.isSubRegister() && "full register expected");
  308. // Pattern-match combinations for which more efficient representations exist.
  309. // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
  310. if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
  311. uint64_t Offset = Op->getArg(0);
  312. uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
  313. if (Offset <= IntMax) {
  314. SignedOffset = Offset;
  315. ExprCursor.take();
  316. }
  317. }
  318. // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
  319. // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
  320. // If Reg is a subregister we need to mask it out before subtracting.
  321. if (Op && Op->getOp() == dwarf::DW_OP_constu) {
  322. uint64_t Offset = Op->getArg(0);
  323. uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
  324. auto N = ExprCursor.peekNext();
  325. if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) {
  326. SignedOffset = Offset;
  327. ExprCursor.consume(2);
  328. } else if (N && N->getOp() == dwarf::DW_OP_minus &&
  329. !SubRegisterSizeInBits && Offset <= IntMax + 1) {
  330. SignedOffset = -static_cast<int64_t>(Offset);
  331. ExprCursor.consume(2);
  332. }
  333. }
  334. if (FBReg)
  335. addFBReg(SignedOffset);
  336. else
  337. addBReg(Reg.DwarfRegNo, SignedOffset);
  338. DwarfRegs.clear();
  339. // If we need to mask out a subregister, do it now, unless the next
  340. // operation would emit an OpPiece anyway.
  341. auto NextOp = ExprCursor.peek();
  342. if (SubRegisterSizeInBits && NextOp &&
  343. (NextOp->getOp() != dwarf::DW_OP_LLVM_fragment))
  344. maskSubRegister();
  345. return true;
  346. }
  347. void DwarfExpression::setEntryValueFlags(const MachineLocation &Loc) {
  348. LocationFlags |= EntryValue;
  349. if (Loc.isIndirect())
  350. LocationFlags |= Indirect;
  351. }
  352. void DwarfExpression::setLocation(const MachineLocation &Loc,
  353. const DIExpression *DIExpr) {
  354. if (Loc.isIndirect())
  355. setMemoryLocationKind();
  356. if (DIExpr->isEntryValue())
  357. setEntryValueFlags(Loc);
  358. }
  359. void DwarfExpression::beginEntryValueExpression(
  360. DIExpressionCursor &ExprCursor) {
  361. auto Op = ExprCursor.take();
  362. (void)Op;
  363. assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value);
  364. assert(!IsEmittingEntryValue && "Already emitting entry value?");
  365. assert(Op->getArg(0) == 1 &&
  366. "Can currently only emit entry values covering a single operation");
  367. SavedLocationKind = LocationKind;
  368. LocationKind = Register;
  369. IsEmittingEntryValue = true;
  370. enableTemporaryBuffer();
  371. }
  372. void DwarfExpression::finalizeEntryValue() {
  373. assert(IsEmittingEntryValue && "Entry value not open?");
  374. disableTemporaryBuffer();
  375. emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
  376. // Emit the entry value's size operand.
  377. unsigned Size = getTemporaryBufferSize();
  378. emitUnsigned(Size);
  379. // Emit the entry value's DWARF block operand.
  380. commitTemporaryBuffer();
  381. LocationFlags &= ~EntryValue;
  382. LocationKind = SavedLocationKind;
  383. IsEmittingEntryValue = false;
  384. }
  385. void DwarfExpression::cancelEntryValue() {
  386. assert(IsEmittingEntryValue && "Entry value not open?");
  387. disableTemporaryBuffer();
  388. // The temporary buffer can't be emptied, so for now just assert that nothing
  389. // has been emitted to it.
  390. assert(getTemporaryBufferSize() == 0 &&
  391. "Began emitting entry value block before cancelling entry value");
  392. LocationKind = SavedLocationKind;
  393. IsEmittingEntryValue = false;
  394. }
  395. unsigned DwarfExpression::getOrCreateBaseType(unsigned BitSize,
  396. dwarf::TypeKind Encoding) {
  397. // Reuse the base_type if we already have one in this CU otherwise we
  398. // create a new one.
  399. unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
  400. for (; I != E; ++I)
  401. if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
  402. CU.ExprRefedBaseTypes[I].Encoding == Encoding)
  403. break;
  404. if (I == E)
  405. CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
  406. return I;
  407. }
  408. /// Assuming a well-formed expression, match "DW_OP_deref*
  409. /// DW_OP_LLVM_fragment?".
  410. static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
  411. while (ExprCursor) {
  412. auto Op = ExprCursor.take();
  413. switch (Op->getOp()) {
  414. case dwarf::DW_OP_deref:
  415. case dwarf::DW_OP_LLVM_fragment:
  416. break;
  417. default:
  418. return false;
  419. }
  420. }
  421. return true;
  422. }
  423. void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor) {
  424. addExpression(std::move(ExprCursor),
  425. [](unsigned Idx, DIExpressionCursor &Cursor) -> bool {
  426. llvm_unreachable("unhandled opcode found in expression");
  427. });
  428. }
  429. bool DwarfExpression::addExpression(
  430. DIExpressionCursor &&ExprCursor,
  431. llvm::function_ref<bool(unsigned, DIExpressionCursor &)> InsertArg) {
  432. // Entry values can currently only cover the initial register location,
  433. // and not any other parts of the following DWARF expression.
  434. assert(!IsEmittingEntryValue && "Can't emit entry value around expression");
  435. std::optional<DIExpression::ExprOperand> PrevConvertOp;
  436. while (ExprCursor) {
  437. auto Op = ExprCursor.take();
  438. uint64_t OpNum = Op->getOp();
  439. if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
  440. emitOp(OpNum);
  441. continue;
  442. } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
  443. addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
  444. continue;
  445. }
  446. switch (OpNum) {
  447. case dwarf::DW_OP_LLVM_arg:
  448. if (!InsertArg(Op->getArg(0), ExprCursor)) {
  449. LocationKind = Unknown;
  450. return false;
  451. }
  452. break;
  453. case dwarf::DW_OP_LLVM_fragment: {
  454. unsigned SizeInBits = Op->getArg(1);
  455. unsigned FragmentOffset = Op->getArg(0);
  456. // The fragment offset must have already been adjusted by emitting an
  457. // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
  458. // location.
  459. assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
  460. assert(SizeInBits >= OffsetInBits - FragmentOffset && "size underflow");
  461. // If addMachineReg already emitted DW_OP_piece operations to represent
  462. // a super-register by splicing together sub-registers, subtract the size
  463. // of the pieces that was already emitted.
  464. SizeInBits -= OffsetInBits - FragmentOffset;
  465. // If addMachineReg requested a DW_OP_bit_piece to stencil out a
  466. // sub-register that is smaller than the current fragment's size, use it.
  467. if (SubRegisterSizeInBits)
  468. SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
  469. // Emit a DW_OP_stack_value for implicit location descriptions.
  470. if (isImplicitLocation())
  471. addStackValue();
  472. // Emit the DW_OP_piece.
  473. addOpPiece(SizeInBits, SubRegisterOffsetInBits);
  474. setSubRegisterPiece(0, 0);
  475. // Reset the location description kind.
  476. LocationKind = Unknown;
  477. return true;
  478. }
  479. case dwarf::DW_OP_plus_uconst:
  480. assert(!isRegisterLocation());
  481. emitOp(dwarf::DW_OP_plus_uconst);
  482. emitUnsigned(Op->getArg(0));
  483. break;
  484. case dwarf::DW_OP_plus:
  485. case dwarf::DW_OP_minus:
  486. case dwarf::DW_OP_mul:
  487. case dwarf::DW_OP_div:
  488. case dwarf::DW_OP_mod:
  489. case dwarf::DW_OP_or:
  490. case dwarf::DW_OP_and:
  491. case dwarf::DW_OP_xor:
  492. case dwarf::DW_OP_shl:
  493. case dwarf::DW_OP_shr:
  494. case dwarf::DW_OP_shra:
  495. case dwarf::DW_OP_lit0:
  496. case dwarf::DW_OP_not:
  497. case dwarf::DW_OP_dup:
  498. case dwarf::DW_OP_push_object_address:
  499. case dwarf::DW_OP_over:
  500. emitOp(OpNum);
  501. break;
  502. case dwarf::DW_OP_deref:
  503. assert(!isRegisterLocation());
  504. if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
  505. // Turning this into a memory location description makes the deref
  506. // implicit.
  507. LocationKind = Memory;
  508. else
  509. emitOp(dwarf::DW_OP_deref);
  510. break;
  511. case dwarf::DW_OP_constu:
  512. assert(!isRegisterLocation());
  513. emitConstu(Op->getArg(0));
  514. break;
  515. case dwarf::DW_OP_consts:
  516. assert(!isRegisterLocation());
  517. emitOp(dwarf::DW_OP_consts);
  518. emitSigned(Op->getArg(0));
  519. break;
  520. case dwarf::DW_OP_LLVM_convert: {
  521. unsigned BitSize = Op->getArg(0);
  522. dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
  523. if (DwarfVersion >= 5 && CU.getDwarfDebug().useOpConvert()) {
  524. emitOp(dwarf::DW_OP_convert);
  525. // If targeting a location-list; simply emit the index into the raw
  526. // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
  527. // fitted with means to extract it later.
  528. // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
  529. // (containing the index and a resolve mechanism during emit) into the
  530. // DIE value list.
  531. emitBaseTypeRef(getOrCreateBaseType(BitSize, Encoding));
  532. } else {
  533. if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
  534. if (Encoding == dwarf::DW_ATE_signed)
  535. emitLegacySExt(PrevConvertOp->getArg(0));
  536. else if (Encoding == dwarf::DW_ATE_unsigned)
  537. emitLegacyZExt(PrevConvertOp->getArg(0));
  538. PrevConvertOp = std::nullopt;
  539. } else {
  540. PrevConvertOp = Op;
  541. }
  542. }
  543. break;
  544. }
  545. case dwarf::DW_OP_stack_value:
  546. LocationKind = Implicit;
  547. break;
  548. case dwarf::DW_OP_swap:
  549. assert(!isRegisterLocation());
  550. emitOp(dwarf::DW_OP_swap);
  551. break;
  552. case dwarf::DW_OP_xderef:
  553. assert(!isRegisterLocation());
  554. emitOp(dwarf::DW_OP_xderef);
  555. break;
  556. case dwarf::DW_OP_deref_size:
  557. emitOp(dwarf::DW_OP_deref_size);
  558. emitData1(Op->getArg(0));
  559. break;
  560. case dwarf::DW_OP_LLVM_tag_offset:
  561. TagOffset = Op->getArg(0);
  562. break;
  563. case dwarf::DW_OP_regx:
  564. emitOp(dwarf::DW_OP_regx);
  565. emitUnsigned(Op->getArg(0));
  566. break;
  567. case dwarf::DW_OP_bregx:
  568. emitOp(dwarf::DW_OP_bregx);
  569. emitUnsigned(Op->getArg(0));
  570. emitSigned(Op->getArg(1));
  571. break;
  572. default:
  573. llvm_unreachable("unhandled opcode found in expression");
  574. }
  575. }
  576. if (isImplicitLocation() && !isParameterValue())
  577. // Turn this into an implicit location description.
  578. addStackValue();
  579. return true;
  580. }
  581. /// add masking operations to stencil out a subregister.
  582. void DwarfExpression::maskSubRegister() {
  583. assert(SubRegisterSizeInBits && "no subregister was registered");
  584. if (SubRegisterOffsetInBits > 0)
  585. addShr(SubRegisterOffsetInBits);
  586. uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
  587. addAnd(Mask);
  588. }
  589. void DwarfExpression::finalize() {
  590. assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
  591. // Emit any outstanding DW_OP_piece operations to mask out subregisters.
  592. if (SubRegisterSizeInBits == 0)
  593. return;
  594. // Don't emit a DW_OP_piece for a subregister at offset 0.
  595. if (SubRegisterOffsetInBits == 0)
  596. return;
  597. addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
  598. }
  599. void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
  600. if (!Expr || !Expr->isFragment())
  601. return;
  602. uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
  603. assert(FragmentOffset >= OffsetInBits &&
  604. "overlapping or duplicate fragments");
  605. if (FragmentOffset > OffsetInBits)
  606. addOpPiece(FragmentOffset - OffsetInBits);
  607. OffsetInBits = FragmentOffset;
  608. }
  609. void DwarfExpression::emitLegacySExt(unsigned FromBits) {
  610. // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
  611. emitOp(dwarf::DW_OP_dup);
  612. emitOp(dwarf::DW_OP_constu);
  613. emitUnsigned(FromBits - 1);
  614. emitOp(dwarf::DW_OP_shr);
  615. emitOp(dwarf::DW_OP_lit0);
  616. emitOp(dwarf::DW_OP_not);
  617. emitOp(dwarf::DW_OP_mul);
  618. emitOp(dwarf::DW_OP_constu);
  619. emitUnsigned(FromBits);
  620. emitOp(dwarf::DW_OP_shl);
  621. emitOp(dwarf::DW_OP_or);
  622. }
  623. void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
  624. // Heuristic to decide the most efficient encoding.
  625. // A ULEB can encode 7 1-bits per byte.
  626. if (FromBits / 7 < 1+1+1+1+1) {
  627. // (X & (1 << FromBits - 1))
  628. emitOp(dwarf::DW_OP_constu);
  629. emitUnsigned((1ULL << FromBits) - 1);
  630. } else {
  631. // Note that the DWARF 4 stack consists of pointer-sized elements,
  632. // so technically it doesn't make sense to shift left more than 64
  633. // bits. We leave that for the consumer to decide though. LLDB for
  634. // example uses APInt for the stack elements and can still deal
  635. // with this.
  636. emitOp(dwarf::DW_OP_lit1);
  637. emitOp(dwarf::DW_OP_constu);
  638. emitUnsigned(FromBits);
  639. emitOp(dwarf::DW_OP_shl);
  640. emitOp(dwarf::DW_OP_lit1);
  641. emitOp(dwarf::DW_OP_minus);
  642. }
  643. emitOp(dwarf::DW_OP_and);
  644. }
  645. void DwarfExpression::addWasmLocation(unsigned Index, uint64_t Offset) {
  646. emitOp(dwarf::DW_OP_WASM_location);
  647. emitUnsigned(Index == 4/*TI_LOCAL_INDIRECT*/ ? 0/*TI_LOCAL*/ : Index);
  648. emitUnsigned(Offset);
  649. if (Index == 4 /*TI_LOCAL_INDIRECT*/) {
  650. assert(LocationKind == Unknown);
  651. LocationKind = Memory;
  652. } else {
  653. assert(LocationKind == Implicit || LocationKind == Unknown);
  654. LocationKind = Implicit;
  655. }
  656. }