gf_5vect_mad_avx512_gfni.asm 6.4 KB

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  1. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  2. ; Copyright(c) 2023 Intel Corporation All rights reserved.
  3. ;
  4. ; Redistribution and use in source and binary forms, with or without
  5. ; modification, are permitted provided that the following conditions
  6. ; are met:
  7. ; * Redistributions of source code must retain the above copyright
  8. ; notice, this list of conditions and the following disclaimer.
  9. ; * Redistributions in binary form must reproduce the above copyright
  10. ; notice, this list of conditions and the following disclaimer in
  11. ; the documentation and/or other materials provided with the
  12. ; distribution.
  13. ; * Neither the name of Intel Corporation nor the names of its
  14. ; contributors may be used to endorse or promote products derived
  15. ; from this software without specific prior written permission.
  16. ;
  17. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20. ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21. ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22. ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23. ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24. ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25. ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26. ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29. ;;;
  30. ;;; gf_5vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest);
  31. ;;;
  32. %include "reg_sizes.asm"
  33. %include "gf_vect_gfni.inc"
  34. %if AS_FEATURE_LEVEL >= 10
  35. %ifidn __OUTPUT_FORMAT__, elf64
  36. %define arg0 rdi
  37. %define arg1 rsi
  38. %define arg2 rdx
  39. %define arg3 rcx
  40. %define arg4 r8
  41. %define arg5 r9
  42. %define tmp r11
  43. %define tmp2 r10
  44. %define func(x) x: endbranch
  45. %define FUNC_SAVE
  46. %define FUNC_RESTORE
  47. %endif
  48. %ifidn __OUTPUT_FORMAT__, win64
  49. %define arg0 rcx
  50. %define arg1 rdx
  51. %define arg2 r8
  52. %define arg3 r9
  53. %define arg4 r12
  54. %define arg5 r13
  55. %define tmp r11
  56. %define tmp2 r10
  57. %define stack_size 16*10 + 3*8
  58. %define arg(x) [rsp + stack_size + 8 + 8*x]
  59. %define func(x) proc_frame x
  60. %macro FUNC_SAVE 0
  61. sub rsp, stack_size
  62. vmovdqa [rsp + 16*0], xmm6
  63. vmovdqa [rsp + 16*1], xmm7
  64. vmovdqa [rsp + 16*2], xmm8
  65. vmovdqa [rsp + 16*3], xmm9
  66. vmovdqa [rsp + 16*4], xmm10
  67. vmovdqa [rsp + 16*5], xmm11
  68. vmovdqa [rsp + 16*6], xmm12
  69. vmovdqa [rsp + 16*7], xmm13
  70. vmovdqa [rsp + 16*8], xmm14
  71. vmovdqa [rsp + 16*9], xmm15
  72. mov [rsp + 10*16 + 0*8], r12
  73. mov [rsp + 10*16 + 1*8], r13
  74. end_prolog
  75. mov arg4, arg(4)
  76. mov arg5, arg(5)
  77. %endmacro
  78. %macro FUNC_RESTORE 0
  79. vmovdqa xmm6, [rsp + 16*0]
  80. vmovdqa xmm7, [rsp + 16*1]
  81. vmovdqa xmm8, [rsp + 16*2]
  82. vmovdqa xmm9, [rsp + 16*3]
  83. vmovdqa xmm10, [rsp + 16*4]
  84. vmovdqa xmm11, [rsp + 16*5]
  85. vmovdqa xmm12, [rsp + 16*6]
  86. vmovdqa xmm13, [rsp + 16*7]
  87. vmovdqa xmm14, [rsp + 16*8]
  88. vmovdqa xmm15, [rsp + 16*9]
  89. mov r12, [rsp + 10*16 + 0*8]
  90. mov r13, [rsp + 10*16 + 1*8]
  91. add rsp, stack_size
  92. %endmacro
  93. %endif
  94. %define len arg0
  95. %define vec arg1
  96. %define vec_i arg2
  97. %define mul_array arg3
  98. %define src arg4
  99. %define dest1 arg5
  100. %define pos rax
  101. %define dest2 tmp2
  102. %define dest3 mul_array
  103. %define dest4 vec
  104. %define dest5 vec_i
  105. %ifndef EC_ALIGNED_ADDR
  106. ;;; Use Un-aligned load/store
  107. %define XLDR vmovdqu8
  108. %define XSTR vmovdqu8
  109. %else
  110. ;;; Use Non-temporal load/stor
  111. %ifdef NO_NT_LDST
  112. %define XLDR vmovdqa64
  113. %define XSTR vmovdqa64
  114. %else
  115. %define XLDR vmovntdqa
  116. %define XSTR vmovntdq
  117. %endif
  118. %endif
  119. default rel
  120. [bits 64]
  121. section .text
  122. %define x0 zmm0
  123. %define xd1 zmm1
  124. %define xd2 zmm2
  125. %define xd3 zmm3
  126. %define xd4 zmm4
  127. %define xd5 zmm5
  128. %define xgft1 zmm6
  129. %define xgft2 zmm7
  130. %define xgft3 zmm8
  131. %define xgft4 zmm9
  132. %define xgft5 zmm10
  133. %define xret1 zmm11
  134. %define xret2 zmm12
  135. %define xret3 zmm13
  136. %define xret4 zmm14
  137. %define xret5 zmm15
  138. ;;
  139. ;; Encodes 64 bytes of a single source into 5x 64 bytes (parity disks)
  140. ;;
  141. %macro ENCODE_64B_5 0-1
  142. %define %%KMASK %1
  143. %if %0 == 1
  144. vmovdqu8 x0{%%KMASK}, [src + pos] ;Get next source vector
  145. vmovdqu8 xd1{%%KMASK}, [dest1 + pos] ;Get next dest vector
  146. vmovdqu8 xd2{%%KMASK}, [dest2 + pos] ;Get next dest vector
  147. vmovdqu8 xd3{%%KMASK}, [dest3 + pos] ;Get next dest vector
  148. vmovdqu8 xd4{%%KMASK}, [dest4 + pos] ;Get next dest vector
  149. vmovdqu8 xd5{%%KMASK}, [dest5 + pos] ;Get next dest vector
  150. %else
  151. XLDR x0, [src + pos] ;Get next source vector
  152. XLDR xd1, [dest1 + pos] ;Get next dest vector
  153. XLDR xd2, [dest2 + pos] ;Get next dest vector
  154. XLDR xd3, [dest3 + pos] ;Get next dest vector
  155. XLDR xd4, [dest4 + pos] ;Get next dest vector
  156. XLDR xd5, [dest5 + pos] ;Get next dest vector
  157. %endif
  158. GF_MUL_XOR EVEX, x0, xgft1, xret1, xd1, xgft2, xret2, xd2, xgft3, xret3, xd3, \
  159. xgft4, xret4, xd4, xgft5, xret5, xd5
  160. %if %0 == 1
  161. vmovdqu8 [dest1 + pos]{%%KMASK}, xd1
  162. vmovdqu8 [dest2 + pos]{%%KMASK}, xd2
  163. vmovdqu8 [dest3 + pos]{%%KMASK}, xd3
  164. vmovdqu8 [dest4 + pos]{%%KMASK}, xd4
  165. vmovdqu8 [dest5 + pos]{%%KMASK}, xd5
  166. %else
  167. XSTR [dest1 + pos], xd1
  168. XSTR [dest2 + pos], xd2
  169. XSTR [dest3 + pos], xd3
  170. XSTR [dest4 + pos], xd4
  171. XSTR [dest5 + pos], xd5
  172. %endif
  173. %endmacro
  174. align 16
  175. global gf_5vect_mad_avx512_gfni, function
  176. func(gf_5vect_mad_avx512_gfni)
  177. FUNC_SAVE
  178. xor pos, pos
  179. shl vec_i, 3 ;Multiply by 8
  180. shl vec, 3 ;Multiply by 8
  181. lea tmp, [mul_array + vec_i]
  182. vbroadcastf32x2 xgft1, [tmp]
  183. vbroadcastf32x2 xgft2, [tmp + vec]
  184. vbroadcastf32x2 xgft3, [tmp + vec*2]
  185. vbroadcastf32x2 xgft5, [tmp + vec*4]
  186. add tmp, vec
  187. vbroadcastf32x2 xgft4, [tmp + vec*2]
  188. mov dest2, [dest1 + 8]
  189. mov dest3, [dest1 + 2*8] ; reuse mul_array
  190. mov dest4, [dest1 + 3*8] ; reuse vec
  191. mov dest5, [dest1 + 4*8] ; reuse vec_i
  192. mov dest1, [dest1]
  193. cmp len, 64
  194. jl .len_lt_64
  195. .loop64:
  196. ENCODE_64B_5
  197. add pos, 64 ;Loop on 64 bytes at a time
  198. sub len, 64
  199. cmp len, 64
  200. jge .loop64
  201. .len_lt_64:
  202. cmp len, 0
  203. jle .exit
  204. xor tmp, tmp
  205. bts tmp, len
  206. dec tmp
  207. kmovq k1, tmp
  208. ENCODE_64B_5 k1
  209. .exit:
  210. vzeroupper
  211. FUNC_RESTORE
  212. ret
  213. endproc_frame
  214. %endif ; if AS_FEATURE_LEVEL >= 10