gf_2vect_mad_avx512_gfni.asm 4.8 KB

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  1. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  2. ; Copyright(c) 2023 Intel Corporation All rights reserved.
  3. ;
  4. ; Redistribution and use in source and binary forms, with or without
  5. ; modification, are permitted provided that the following conditions
  6. ; are met:
  7. ; * Redistributions of source code must retain the above copyright
  8. ; notice, this list of conditions and the following disclaimer.
  9. ; * Redistributions in binary form must reproduce the above copyright
  10. ; notice, this list of conditions and the following disclaimer in
  11. ; the documentation and/or other materials provided with the
  12. ; distribution.
  13. ; * Neither the name of Intel Corporation nor the names of its
  14. ; contributors may be used to endorse or promote products derived
  15. ; from this software without specific prior written permission.
  16. ;
  17. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20. ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21. ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22. ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23. ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24. ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25. ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26. ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29. ;;;
  30. ;;; gf_2vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest);
  31. ;;;
  32. %include "reg_sizes.asm"
  33. %include "gf_vect_gfni.inc"
  34. %if AS_FEATURE_LEVEL >= 10
  35. %ifidn __OUTPUT_FORMAT__, elf64
  36. %define arg0 rdi
  37. %define arg1 rsi
  38. %define arg2 rdx
  39. %define arg3 rcx
  40. %define arg4 r8
  41. %define arg5 r9
  42. %define tmp r11
  43. %define tmp2 r10
  44. %define func(x) x: endbranch
  45. %define FUNC_SAVE
  46. %define FUNC_RESTORE
  47. %endif
  48. %ifidn __OUTPUT_FORMAT__, win64
  49. %define arg0 rcx
  50. %define arg1 rdx
  51. %define arg2 r8
  52. %define arg3 r9
  53. %define arg4 r12
  54. %define arg5 r13
  55. %define tmp r11
  56. %define tmp2 r10
  57. %define stack_size 16 + 3*8 ; must be an odd multiple of 8
  58. %define arg(x) [rsp + stack_size + 8 + 8*x]
  59. %define func(x) proc_frame x
  60. %macro FUNC_SAVE 0
  61. sub rsp, stack_size
  62. vmovdqa [rsp + 16*0], xmm6
  63. mov [rsp + 16 + 0*8], r12
  64. mov [rsp + 16 + 1*8], r13
  65. end_prolog
  66. mov arg4, arg(4)
  67. mov arg5, arg(5)
  68. %endmacro
  69. %macro FUNC_RESTORE 0
  70. vmovdqa xmm6, [rsp + 16*0]
  71. mov r12, [rsp + 16 + 0*8]
  72. mov r13, [rsp + 16 + 1*8]
  73. add rsp, stack_size
  74. %endmacro
  75. %endif
  76. %define len arg0
  77. %define vec arg1
  78. %define vec_i arg2
  79. %define mul_array arg3
  80. %define src arg4
  81. %define dest1 arg5
  82. %define pos rax
  83. %define dest2 tmp2
  84. %ifndef EC_ALIGNED_ADDR
  85. ;;; Use Un-aligned load/store
  86. %define XLDR vmovdqu8
  87. %define XSTR vmovdqu8
  88. %else
  89. ;;; Use Non-temporal load/stor
  90. %ifdef NO_NT_LDST
  91. %define XLDR vmovdqa64
  92. %define XSTR vmovdqa64
  93. %else
  94. %define XLDR vmovntdqa
  95. %define XSTR vmovntdq
  96. %endif
  97. %endif
  98. default rel
  99. [bits 64]
  100. section .text
  101. %define x0 zmm0
  102. %define xd1 zmm1
  103. %define xd2 zmm2
  104. %define xgft1 zmm3
  105. %define xgft2 zmm4
  106. %define xret1 zmm5
  107. %define xret2 zmm6
  108. ;;
  109. ;; Encodes 64 bytes of a single source into 2x 64 bytes (parity disks)
  110. ;;
  111. %macro ENCODE_64B_2 0-1
  112. %define %%KMASK %1
  113. %if %0 == 1
  114. vmovdqu8 x0{%%KMASK}, [src + pos] ;Get next source vector
  115. vmovdqu8 xd1{%%KMASK}, [dest1 + pos] ;Get next dest vector
  116. vmovdqu8 xd2{%%KMASK}, [dest2 + pos] ;Get next dest vector
  117. %else
  118. XLDR x0, [src + pos] ;Get next source vector
  119. XLDR xd1, [dest1 + pos] ;Get next dest vector
  120. XLDR xd2, [dest2 + pos] ;Get next dest vector
  121. %endif
  122. GF_MUL_XOR EVEX, x0, xgft1, xret1, xd1, xgft2, xret2, xd2
  123. %if %0 == 1
  124. vmovdqu8 [dest1 + pos]{%%KMASK}, xd1
  125. vmovdqu8 [dest2 + pos]{%%KMASK}, xd2
  126. %else
  127. XSTR [dest1 + pos], xd1
  128. XSTR [dest2 + pos], xd2
  129. %endif
  130. %endmacro
  131. align 16
  132. global gf_2vect_mad_avx512_gfni, function
  133. func(gf_2vect_mad_avx512_gfni)
  134. FUNC_SAVE
  135. xor pos, pos
  136. shl vec_i, 3 ;Multiply by 8
  137. shl vec, 3
  138. lea tmp, [mul_array + vec_i]
  139. vbroadcastf32x2 xgft1, [tmp]
  140. vbroadcastf32x2 xgft2, [tmp + vec]
  141. mov dest2, [dest1 + 8] ; reuse mul_array
  142. mov dest1, [dest1]
  143. cmp len, 64
  144. jl .len_lt_64
  145. .loop64:
  146. ENCODE_64B_2
  147. add pos, 64 ;Loop on 64 bytes at a time
  148. sub len, 64
  149. cmp len, 64
  150. jge .loop64
  151. .len_lt_64:
  152. cmp len, 0
  153. jle .exit
  154. xor tmp, tmp
  155. bts tmp, len
  156. dec tmp
  157. kmovq k1, tmp
  158. ENCODE_64B_2 k1
  159. .exit:
  160. vzeroupper
  161. FUNC_RESTORE
  162. ret
  163. endproc_frame
  164. %endif ; if AS_FEATURE_LEVEL >= 10