gf_2vect_dot_prod_avx.asm 7.8 KB

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  1. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  2. ; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
  3. ;
  4. ; Redistribution and use in source and binary forms, with or without
  5. ; modification, are permitted provided that the following conditions
  6. ; are met:
  7. ; * Redistributions of source code must retain the above copyright
  8. ; notice, this list of conditions and the following disclaimer.
  9. ; * Redistributions in binary form must reproduce the above copyright
  10. ; notice, this list of conditions and the following disclaimer in
  11. ; the documentation and/or other materials provided with the
  12. ; distribution.
  13. ; * Neither the name of Intel Corporation nor the names of its
  14. ; contributors may be used to endorse or promote products derived
  15. ; from this software without specific prior written permission.
  16. ;
  17. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20. ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21. ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22. ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23. ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24. ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25. ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26. ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29. ;;;
  30. ;;; gf_2vect_dot_prod_avx(len, vec, *g_tbls, **buffs, **dests);
  31. ;;;
  32. %include "reg_sizes.asm"
  33. %ifidn __OUTPUT_FORMAT__, elf64
  34. %define arg0 rdi
  35. %define arg1 rsi
  36. %define arg2 rdx
  37. %define arg3 rcx
  38. %define arg4 r8
  39. %define arg5 r9
  40. %define tmp r11
  41. %define tmp2 r10
  42. %define tmp3 r9
  43. %define tmp4 r12 ; must be saved and restored
  44. %define return rax
  45. %macro SLDR 2
  46. %endmacro
  47. %define SSTR SLDR
  48. %define PS 8
  49. %define LOG_PS 3
  50. %define func(x) x: endbranch
  51. %macro FUNC_SAVE 0
  52. push r12
  53. %endmacro
  54. %macro FUNC_RESTORE 0
  55. pop r12
  56. %endmacro
  57. %endif
  58. %ifidn __OUTPUT_FORMAT__, win64
  59. %define arg0 rcx
  60. %define arg1 rdx
  61. %define arg2 r8
  62. %define arg3 r9
  63. %define arg4 r12 ; must be saved, loaded and restored
  64. %define tmp r11
  65. %define tmp2 r10
  66. %define tmp3 r13 ; must be saved and restored
  67. %define tmp4 r14 ; must be saved and restored
  68. %define return rax
  69. %macro SLDR 2
  70. %endmacro
  71. %define SSTR SLDR
  72. %define PS 8
  73. %define LOG_PS 3
  74. %define stack_size 3*16 + 3*8 ; must be an odd multiple of 8
  75. %define arg(x) [rsp + stack_size + PS + PS*x]
  76. %define func(x) proc_frame x
  77. %macro FUNC_SAVE 0
  78. alloc_stack stack_size
  79. vmovdqa [rsp + 0*16], xmm6
  80. vmovdqa [rsp + 1*16], xmm7
  81. vmovdqa [rsp + 2*16], xmm8
  82. save_reg r12, 3*16 + 0*8
  83. save_reg r13, 3*16 + 1*8
  84. save_reg r14, 3*16 + 2*8
  85. end_prolog
  86. mov arg4, arg(4)
  87. %endmacro
  88. %macro FUNC_RESTORE 0
  89. vmovdqa xmm6, [rsp + 0*16]
  90. vmovdqa xmm7, [rsp + 1*16]
  91. vmovdqa xmm8, [rsp + 2*16]
  92. mov r12, [rsp + 3*16 + 0*8]
  93. mov r13, [rsp + 3*16 + 1*8]
  94. mov r14, [rsp + 3*16 + 2*8]
  95. add rsp, stack_size
  96. %endmacro
  97. %endif
  98. %ifidn __OUTPUT_FORMAT__, elf32
  99. ;;;================== High Address;
  100. ;;; arg4
  101. ;;; arg3
  102. ;;; arg2
  103. ;;; arg1
  104. ;;; arg0
  105. ;;; return
  106. ;;;<================= esp of caller
  107. ;;; ebp
  108. ;;;<================= ebp = esp
  109. ;;; var0
  110. ;;; esi
  111. ;;; edi
  112. ;;; ebx
  113. ;;;<================= esp of callee
  114. ;;;
  115. ;;;================== Low Address;
  116. %define PS 4
  117. %define LOG_PS 2
  118. %define func(x) x: endbranch
  119. %define arg(x) [ebp + PS*2 + PS*x]
  120. %define var(x) [ebp - PS - PS*x]
  121. %define trans ecx
  122. %define trans2 esi
  123. %define arg0 trans ;trans and trans2 are for the variables in stack
  124. %define arg0_m arg(0)
  125. %define arg1 ebx
  126. %define arg2 arg2_m
  127. %define arg2_m arg(2)
  128. %define arg3 trans
  129. %define arg3_m arg(3)
  130. %define arg4 trans
  131. %define arg4_m arg(4)
  132. %define tmp edx
  133. %define tmp2 edi
  134. %define tmp3 trans2
  135. %define tmp4 trans2
  136. %define tmp4_m var(0)
  137. %define return eax
  138. %macro SLDR 2 ;; stack load/restore
  139. mov %1, %2
  140. %endmacro
  141. %define SSTR SLDR
  142. %macro FUNC_SAVE 0
  143. push ebp
  144. mov ebp, esp
  145. sub esp, PS*1 ;1 local variable
  146. push esi
  147. push edi
  148. push ebx
  149. mov arg1, arg(1)
  150. %endmacro
  151. %macro FUNC_RESTORE 0
  152. pop ebx
  153. pop edi
  154. pop esi
  155. add esp, PS*1 ;1 local variable
  156. pop ebp
  157. %endmacro
  158. %endif ; output formats
  159. %define len arg0
  160. %define vec arg1
  161. %define mul_array arg2
  162. %define src arg3
  163. %define dest1 arg4
  164. %define vec_i tmp2
  165. %define ptr tmp3
  166. %define dest2 tmp4
  167. %define pos return
  168. %ifidn PS,4 ;32-bit code
  169. %define len_m arg0_m
  170. %define src_m arg3_m
  171. %define dest1_m arg4_m
  172. %define dest2_m tmp4_m
  173. %endif
  174. %ifndef EC_ALIGNED_ADDR
  175. ;;; Use Un-aligned load/store
  176. %define XLDR vmovdqu
  177. %define XSTR vmovdqu
  178. %else
  179. ;;; Use Non-temporal load/stor
  180. %ifdef NO_NT_LDST
  181. %define XLDR vmovdqa
  182. %define XSTR vmovdqa
  183. %else
  184. %define XLDR vmovntdqa
  185. %define XSTR vmovntdq
  186. %endif
  187. %endif
  188. %ifidn PS,8 ; 64-bit code
  189. default rel
  190. [bits 64]
  191. %endif
  192. section .text
  193. %ifidn PS,8 ;64-bit code
  194. %define xmask0f xmm8
  195. %define xgft1_lo xmm7
  196. %define xgft1_hi xmm6
  197. %define xgft2_lo xmm5
  198. %define xgft2_hi xmm4
  199. %define x0 xmm0
  200. %define xtmpa xmm1
  201. %define xp1 xmm2
  202. %define xp2 xmm3
  203. %else ;32-bit code
  204. %define xmask0f xmm4
  205. %define xgft1_lo xmm7
  206. %define xgft1_hi xmm6
  207. %define xgft2_lo xgft1_lo
  208. %define xgft2_hi xgft1_hi
  209. %define x0 xmm0
  210. %define xtmpa xmm1
  211. %define xp1 xmm2
  212. %define xp2 xmm3
  213. %endif
  214. align 16
  215. global gf_2vect_dot_prod_avx, function
  216. func(gf_2vect_dot_prod_avx)
  217. FUNC_SAVE
  218. SLDR len, len_m
  219. sub len, 16
  220. SSTR len_m, len
  221. jl .return_fail
  222. xor pos, pos
  223. vmovdqa xmask0f, [mask0f] ;Load mask of lower nibble in each byte
  224. sal vec, LOG_PS ;vec *= PS. Make vec_i count by PS
  225. SLDR dest1, dest1_m
  226. mov dest2, [dest1+PS]
  227. SSTR dest2_m, dest2
  228. mov dest1, [dest1]
  229. SSTR dest1_m, dest1
  230. .loop16:
  231. vpxor xp1, xp1
  232. vpxor xp2, xp2
  233. mov tmp, mul_array
  234. xor vec_i, vec_i
  235. .next_vect:
  236. SLDR src, src_m
  237. mov ptr, [src+vec_i]
  238. vmovdqu xgft1_lo, [tmp] ;Load array Ax{00}, Ax{01}, ..., Ax{0f}
  239. vmovdqu xgft1_hi, [tmp+16] ; " Ax{00}, Ax{10}, ..., Ax{f0}
  240. %ifidn PS,8 ; 64-bit code
  241. vmovdqu xgft2_lo, [tmp+vec*(32/PS)] ;Load array Bx{00}, Bx{01}, ..., Bx{0f}
  242. vmovdqu xgft2_hi, [tmp+vec*(32/PS)+16] ; " Bx{00}, Bx{10}, ..., Bx{f0}
  243. add tmp, 32
  244. add vec_i, PS
  245. %endif
  246. XLDR x0, [ptr+pos] ;Get next source vector
  247. vpand xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
  248. vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
  249. vpand x0, x0, xmask0f ;Mask high src nibble in bits 4-0
  250. vpshufb xgft1_hi, x0 ;Lookup mul table of high nibble
  251. vpshufb xgft1_lo, xtmpa ;Lookup mul table of low nibble
  252. vpxor xgft1_hi, xgft1_lo ;GF add high and low partials
  253. vpxor xp1, xgft1_hi ;xp1 += partial
  254. %ifidn PS,4 ; 32-bit code
  255. vmovdqu xgft2_lo, [tmp+vec*(32/PS)] ;Load array Bx{00}, Bx{01}, ..., Bx{0f}
  256. vmovdqu xgft2_hi, [tmp+vec*(32/PS)+16] ; " Bx{00}, Bx{10}, ..., Bx{f0}
  257. add tmp, 32
  258. add vec_i, PS
  259. %endif
  260. vpshufb xgft2_hi, x0 ;Lookup mul table of high nibble
  261. vpshufb xgft2_lo, xtmpa ;Lookup mul table of low nibble
  262. vpxor xgft2_hi, xgft2_lo ;GF add high and low partials
  263. vpxor xp2, xgft2_hi ;xp2 += partial
  264. cmp vec_i, vec
  265. jl .next_vect
  266. SLDR dest1, dest1_m
  267. SLDR dest2, dest2_m
  268. XSTR [dest1+pos], xp1
  269. XSTR [dest2+pos], xp2
  270. SLDR len, len_m
  271. add pos, 16 ;Loop on 16 bytes at a time
  272. cmp pos, len
  273. jle .loop16
  274. lea tmp, [len + 16]
  275. cmp pos, tmp
  276. je .return_pass
  277. ;; Tail len
  278. mov pos, len ;Overlapped offset length-16
  279. jmp .loop16 ;Do one more overlap pass
  280. .return_pass:
  281. mov return, 0
  282. FUNC_RESTORE
  283. ret
  284. .return_fail:
  285. mov return, 1
  286. FUNC_RESTORE
  287. ret
  288. endproc_frame
  289. section .data
  290. align 16
  291. mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f