X86InstrSVM.td 2.7 KB

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  1. //===-- X86InstrSVM.td - SVM Instruction Set Extension -----*- tablegen -*-===//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //===----------------------------------------------------------------------===//
  8. //
  9. // This file describes the instructions that make up the AMD SVM instruction
  10. // set.
  11. //
  12. //===----------------------------------------------------------------------===//
  13. //===----------------------------------------------------------------------===//
  14. // SVM instructions
  15. let SchedRW = [WriteSystem] in {
  16. // 0F 01 D9
  17. def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
  18. // 0F 01 DC
  19. def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
  20. // 0F 01 DD
  21. def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
  22. // 0F 01 DE
  23. let Uses = [EAX] in
  24. def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit", []>, TB;
  25. // 0F 01 D8
  26. let Uses = [EAX] in
  27. def VMRUN32 : I<0x01, MRM_D8, (outs), (ins), "vmrun", []>, TB,
  28. Requires<[Not64BitMode]>;
  29. let Uses = [RAX] in
  30. def VMRUN64 : I<0x01, MRM_D8, (outs), (ins), "vmrun", []>, TB,
  31. Requires<[In64BitMode]>;
  32. // 0F 01 DA
  33. let Uses = [EAX] in
  34. def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins), "vmload", []>, TB,
  35. Requires<[Not64BitMode]>;
  36. let Uses = [RAX] in
  37. def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins), "vmload", []>, TB,
  38. Requires<[In64BitMode]>;
  39. // 0F 01 DB
  40. let Uses = [EAX] in
  41. def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins), "vmsave", []>, TB,
  42. Requires<[Not64BitMode]>;
  43. let Uses = [RAX] in
  44. def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins), "vmsave", []>, TB,
  45. Requires<[In64BitMode]>;
  46. // 0F 01 DF
  47. let Uses = [EAX, ECX] in
  48. def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins),
  49. "invlpga", []>, TB, Requires<[Not64BitMode]>;
  50. let Uses = [RAX, ECX] in
  51. def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins),
  52. "invlpga", []>, TB, Requires<[In64BitMode]>;
  53. } // SchedRW
  54. def : InstAlias<"skinit\t{%eax|eax}", (SKINIT), 0>;
  55. def : InstAlias<"vmrun\t{%eax|eax}", (VMRUN32), 0>, Requires<[Not64BitMode]>;
  56. def : InstAlias<"vmrun\t{%rax|rax}", (VMRUN64), 0>, Requires<[In64BitMode]>;
  57. def : InstAlias<"vmload\t{%eax|eax}", (VMLOAD32), 0>, Requires<[Not64BitMode]>;
  58. def : InstAlias<"vmload\t{%rax|rax}", (VMLOAD64), 0>, Requires<[In64BitMode]>;
  59. def : InstAlias<"vmsave\t{%eax|eax}", (VMSAVE32), 0>, Requires<[Not64BitMode]>;
  60. def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
  61. def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>;
  62. def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;