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RISCVProcessors.td

RISCVProcessors.td 7.3 KB
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  1. //===-- RISCVProcessors.td - RISCV Processors --------------*- tablegen -*-===//
    2. 

  2. //
    3. 

  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
    4. 

  4. // See https://llvm.org/LICENSE.txt for license information.
    5. 

  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
    6. 

  6. //
    7. 

  7. //===----------------------------------------------------------------------===//
    8. 

  8. 

  9. //===----------------------------------------------------------------------===//
    10. 

  10. // RISC-V processors supported.
    11. 

  11. //===----------------------------------------------------------------------===//
    12. 

  12. 

  13. class RISCVProcessorModel<string n,
    14. 

  14.                           SchedMachineModel m,
    15. 

  15.                           list<SubtargetFeature> f,
    16. 

  16.                           list<SubtargetFeature> tunef = [],
    17. 

  17.                           string default_march = "">
    18. 

  18.       :  ProcessorModel<n, m, f, tunef> {
    19. 

  19.   string DefaultMarch = default_march;
    20. 

  20. }
    21. 

  21. 

  22. class RISCVTuneProcessorModel<string n,
    23. 

  23.                               SchedMachineModel m,
    24. 

  24.                               list<SubtargetFeature> tunef = [],
    25. 

  25.                               list<SubtargetFeature> f = []>
    26. 

  26.       : ProcessorModel<n, m, f,tunef>;
    27. 

  27. 

  28. def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
    29. 

  29.                                        NoSchedModel,
    30. 

  30.                                        [Feature32Bit]>;
    31. 

  31. def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
    32. 

  32.                                        NoSchedModel,
    33. 

  33.                                        [Feature64Bit]>;
    34. 

  34. // Support generic for compatibility with other targets. The triple will be used
    35. 

  35. // to change to the appropriate rv32/rv64 version.
    36. 

  36. def : ProcessorModel<"generic", NoSchedModel, []>;
    37. 

  37. 

  38. def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
    39. 

  39.                                       RocketModel,
    40. 

  40.                                       [Feature32Bit]>;
    41. 

  41. def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
    42. 

  42.                                       RocketModel,
    43. 

  43.                                       [Feature64Bit]>;
    44. 

  44. def ROCKET : RISCVTuneProcessorModel<"rocket",
    45. 

  45.                                      RocketModel>;
    46. 

  46. 

  47. def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
    48. 

  48.                                        SiFive7Model,
    49. 

  49.                                        [TuneSiFive7]>;
    50. 

  50. 

  51. def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
    52. 

  52.                                      RocketModel,
    53. 

  53.                                      [Feature32Bit,
    54. 

  54.                                       FeatureStdExtM,
    55. 

  55.                                       FeatureStdExtC]>;
    56. 

  56. 

  57. def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
    58. 

  58.                                      RocketModel,
    59. 

  59.                                      [Feature32Bit,
    60. 

  60.                                       FeatureStdExtM,
    61. 

  61.                                       FeatureStdExtA,
    62. 

  62.                                       FeatureStdExtC]>;
    63. 

  63. 

  64. def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
    65. 

  65.                                      RocketModel,
    66. 

  66.                                      [Feature32Bit,
    67. 

  67.                                       FeatureStdExtM,
    68. 

  68.                                       FeatureStdExtA,
    69. 

  69.                                       FeatureStdExtF,
    70. 

  70.                                       FeatureStdExtC]>;
    71. 

  71. 

  72. def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
    73. 

  73.                                      RocketModel,
    74. 

  74.                                      [Feature32Bit,
    75. 

  75.                                       FeatureStdExtM,
    76. 

  76.                                       FeatureStdExtA,
    77. 

  77.                                       FeatureStdExtC]>;
    78. 

  78. 

  79. def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
    80. 

  80.                                      RocketModel,
    81. 

  81.                                      [Feature32Bit,
    82. 

  82.                                       FeatureStdExtM,
    83. 

  83.                                       FeatureStdExtA,
    84. 

  84.                                       FeatureStdExtF,
    85. 

  85.                                       FeatureStdExtC]>;
    86. 

  86. 

  87. def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
    88. 

  88.                                      SiFive7Model,
    89. 

  89.                                      [Feature32Bit,
    90. 

  90.                                       FeatureStdExtM,
    91. 

  91.                                       FeatureStdExtA,
    92. 

  92.                                       FeatureStdExtF,
    93. 

  93.                                       FeatureStdExtC],
    94. 

  94.                                      [TuneSiFive7]>;
    95. 

  95. 

  96. def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
    97. 

  97.                                      RocketModel,
    98. 

  98.                                      [Feature64Bit,
    99. 

  99.                                       FeatureStdExtM,
    100. 

  100.                                       FeatureStdExtA,
    101. 

  101.                                       FeatureStdExtC]>;
    102. 

  102. 

  103. def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
    104. 

  104.                                      RocketModel,
    105. 

  105.                                      [Feature64Bit,
    106. 

  106.                                       FeatureStdExtM,
    107. 

  107.                                       FeatureStdExtA,
    108. 

  108.                                       FeatureStdExtC]>;
    109. 

  109. 

  110. def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
    111. 

  111.                                       RocketModel,
    112. 

  112.                                       [Feature64Bit,
    113. 

  113.                                        FeatureStdExtM,
    114. 

  114.                                        FeatureStdExtA,
    115. 

  115.                                        FeatureStdExtF,
    116. 

  116.                                        FeatureStdExtD,
    117. 

  117.                                        FeatureStdExtC]>;
    118. 

  118. 

  119. def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
    120. 

  120.                                      SiFive7Model,
    121. 

  121.                                      [Feature64Bit,
    122. 

  122.                                       FeatureStdExtM,
    123. 

  123.                                       FeatureStdExtA,
    124. 

  124.                                       FeatureStdExtF,
    125. 

  125.                                       FeatureStdExtD,
    126. 

  126.                                       FeatureStdExtC],
    127. 

  127.                                      [TuneSiFive7]>;
    128. 

  128. 

  129. def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
    130. 

  130.                                      RocketModel,
    131. 

  131.                                      [Feature64Bit,
    132. 

  132.                                       FeatureStdExtM,
    133. 

  133.                                       FeatureStdExtA,
    134. 

  134.                                       FeatureStdExtF,
    135. 

  135.                                       FeatureStdExtD,
    136. 

  136.                                       FeatureStdExtC]>;
    137. 

  137. 

  138. def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
    139. 

  139.                                      SiFive7Model,
    140. 

  140.                                      [Feature64Bit,
    141. 

  141.                                       FeatureStdExtM,
    142. 

  142.                                       FeatureStdExtA,
    143. 

  143.                                       FeatureStdExtF,
    144. 

  144.                                       FeatureStdExtD,
    145. 

  145.                                       FeatureStdExtC],
    146. 

  146.                                      [TuneSiFive7]>;
    147. 

  147. 

  148. def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
    149. 

  149.                                               SyntacoreSCR1Model,
    150. 

  150.                                               [Feature32Bit,
    151. 

  151.                                                FeatureStdExtC],
    152. 

  152.                                               [TuneNoDefaultUnroll]>;
    153. 

  153. 

  154. def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
    155. 

  155.                                              SyntacoreSCR1Model,
    156. 

  156.                                              [Feature32Bit,
    157. 

  157.                                               FeatureStdExtM,
    158. 

  158.                                               FeatureStdExtC],
    159. 

  159.                                              [TuneNoDefaultUnroll]>;
    160.