gf_4vect_mad_avx512.asm 7.6 KB

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  1. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  2. ; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
  3. ;
  4. ; Redistribution and use in source and binary forms, with or without
  5. ; modification, are permitted provided that the following conditions
  6. ; are met:
  7. ; * Redistributions of source code must retain the above copyright
  8. ; notice, this list of conditions and the following disclaimer.
  9. ; * Redistributions in binary form must reproduce the above copyright
  10. ; notice, this list of conditions and the following disclaimer in
  11. ; the documentation and/or other materials provided with the
  12. ; distribution.
  13. ; * Neither the name of Intel Corporation nor the names of its
  14. ; contributors may be used to endorse or promote products derived
  15. ; from this software without specific prior written permission.
  16. ;
  17. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20. ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21. ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22. ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23. ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24. ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25. ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26. ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29. ;;;
  30. ;;; gf_4vect_mad_avx512(len, vec, vec_i, mul_array, src, dest);
  31. ;;;
  32. %include "reg_sizes.asm"
  33. %ifdef HAVE_AS_KNOWS_AVX512
  34. %ifidn __OUTPUT_FORMAT__, elf64
  35. %define arg0 rdi
  36. %define arg1 rsi
  37. %define arg2 rdx
  38. %define arg3 rcx
  39. %define arg4 r8
  40. %define arg5 r9
  41. %define tmp r11
  42. %define return rax
  43. %define func(x) x:
  44. %define FUNC_SAVE
  45. %define FUNC_RESTORE
  46. %endif
  47. %ifidn __OUTPUT_FORMAT__, win64
  48. %define arg0 rcx
  49. %define arg1 rdx
  50. %define arg2 r8
  51. %define arg3 r9
  52. %define arg4 r12
  53. %define arg5 r15
  54. %define tmp r11
  55. %define return rax
  56. %define stack_size 16*10 + 3*8
  57. %define arg(x) [rsp + stack_size + PS + PS*x]
  58. %define func(x) proc_frame x
  59. %macro FUNC_SAVE 0
  60. sub rsp, stack_size
  61. movdqa [rsp+16*0],xmm6
  62. movdqa [rsp+16*1],xmm7
  63. movdqa [rsp+16*2],xmm8
  64. movdqa [rsp+16*3],xmm9
  65. movdqa [rsp+16*4],xmm10
  66. movdqa [rsp+16*5],xmm11
  67. movdqa [rsp+16*6],xmm12
  68. movdqa [rsp+16*7],xmm13
  69. movdqa [rsp+16*8],xmm14
  70. movdqa [rsp+16*9],xmm15
  71. save_reg r12, 10*16 + 0*8
  72. save_reg r15, 10*16 + 1*8
  73. end_prolog
  74. mov arg4, arg(4)
  75. mov arg5, arg(5)
  76. %endmacro
  77. %macro FUNC_RESTORE 0
  78. movdqa xmm6, [rsp+16*0]
  79. movdqa xmm7, [rsp+16*1]
  80. movdqa xmm8, [rsp+16*2]
  81. movdqa xmm9, [rsp+16*3]
  82. movdqa xmm10, [rsp+16*4]
  83. movdqa xmm11, [rsp+16*5]
  84. movdqa xmm12, [rsp+16*6]
  85. movdqa xmm13, [rsp+16*7]
  86. movdqa xmm14, [rsp+16*8]
  87. movdqa xmm15, [rsp+16*9]
  88. mov r12, [rsp + 10*16 + 0*8]
  89. mov r15, [rsp + 10*16 + 1*8]
  90. add rsp, stack_size
  91. %endmacro
  92. %endif
  93. %define PS 8
  94. %define len arg0
  95. %define vec arg1
  96. %define vec_i arg2
  97. %define mul_array arg3
  98. %define src arg4
  99. %define dest1 arg5
  100. %define pos return
  101. %define dest2 mul_array
  102. %define dest3 vec
  103. %define dest4 vec_i
  104. %ifndef EC_ALIGNED_ADDR
  105. ;;; Use Un-aligned load/store
  106. %define XLDR vmovdqu8
  107. %define XSTR vmovdqu8
  108. %else
  109. ;;; Use Non-temporal load/stor
  110. %ifdef NO_NT_LDST
  111. %define XLDR vmovdqa
  112. %define XSTR vmovdqa
  113. %else
  114. %define XLDR vmovntdqa
  115. %define XSTR vmovntdq
  116. %endif
  117. %endif
  118. default rel
  119. [bits 64]
  120. section .text
  121. %define x0 zmm0
  122. %define xtmpa zmm1
  123. %define xtmpl1 zmm2
  124. %define xtmph1 zmm3
  125. %define xtmph2 zmm4
  126. %define xtmph3 zmm5
  127. %define xtmph4 zmm6
  128. %define xgft1_hi zmm7
  129. %define xgft1_lo zmm8
  130. %define xgft1_loy ymm8
  131. %define xgft2_hi zmm9
  132. %define xgft2_lo zmm10
  133. %define xgft2_loy ymm10
  134. %define xgft3_hi zmm11
  135. %define xgft3_lo zmm12
  136. %define xgft3_loy ymm12
  137. %define xgft4_hi zmm13
  138. %define xgft4_lo zmm14
  139. %define xgft4_loy ymm14
  140. %define xd1 zmm15
  141. %define xd2 zmm16
  142. %define xd3 zmm17
  143. %define xd4 zmm18
  144. %define xmask0f zmm19
  145. %define xtmpl2 zmm20
  146. %define xtmpl3 zmm21
  147. %define xtmpl4 zmm22
  148. %define xtmpl5 zmm23
  149. align 16
  150. global gf_4vect_mad_avx512:ISAL_SYM_TYPE_FUNCTION
  151. func(gf_4vect_mad_avx512)
  152. %ifidn __OUTPUT_FORMAT__, macho64
  153. global _gf_4vect_mad_avx512:ISAL_SYM_TYPE_FUNCTION
  154. func(_gf_4vect_mad_avx512)
  155. %endif
  156. FUNC_SAVE
  157. sub len, 64
  158. jl .return_fail
  159. xor pos, pos
  160. mov tmp, 0x0f
  161. vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
  162. sal vec_i, 5 ;Multiply by 32
  163. sal vec, 5 ;Multiply by 32
  164. lea tmp, [mul_array + vec_i]
  165. vmovdqu xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
  166. vmovdqu xgft2_loy, [tmp+vec] ;Load array Bx{00}..{0f}, Bx{00}..{f0}
  167. vmovdqu xgft3_loy, [tmp+2*vec] ;Load array Cx{00}..{0f}, Cx{00}..{f0}
  168. add tmp, vec
  169. vmovdqu xgft4_loy, [tmp+2*vec] ;Load array Dx{00}..{0f}, Dx{00}..{f0}
  170. vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x55
  171. vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x00
  172. vshufi64x2 xgft2_hi, xgft2_lo, xgft2_lo, 0x55
  173. vshufi64x2 xgft2_lo, xgft2_lo, xgft2_lo, 0x00
  174. vshufi64x2 xgft3_hi, xgft3_lo, xgft3_lo, 0x55
  175. vshufi64x2 xgft3_lo, xgft3_lo, xgft3_lo, 0x00
  176. vshufi64x2 xgft4_hi, xgft4_lo, xgft4_lo, 0x55
  177. vshufi64x2 xgft4_lo, xgft4_lo, xgft4_lo, 0x00
  178. mov dest2, [dest1+PS] ; reuse mul_array
  179. mov dest3, [dest1+2*PS] ; reuse vec
  180. mov dest4, [dest1+3*PS] ; reuse vec_i
  181. mov dest1, [dest1]
  182. mov tmp, -1
  183. kmovq k1, tmp
  184. .loop64:
  185. XLDR x0, [src+pos] ;Get next source vector
  186. XLDR xd1, [dest1+pos] ;Get next dest vector
  187. XLDR xd2, [dest2+pos] ;Get next dest vector
  188. XLDR xd3, [dest3+pos] ;Get next dest vector
  189. XLDR xd4, [dest4+pos] ;reuse xtmpl1. Get next dest vector
  190. vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
  191. vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
  192. vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
  193. ; dest1
  194. vpshufb xtmph1 {k1}{z}, xgft1_hi, x0 ;Lookup mul table of high nibble
  195. vpshufb xtmpl1 {k1}{z}, xgft1_lo, xtmpa ;Lookup mul table of low nibble
  196. vpxorq xtmph1, xtmph1, xtmpl1 ;GF add high and low partials
  197. vpxorq xd1, xd1, xtmph1 ;xd1 += partial
  198. ; dest2
  199. vpshufb xtmph2 {k1}{z}, xgft2_hi, x0 ;Lookup mul table of high nibble
  200. vpshufb xtmpl2 {k1}{z}, xgft2_lo, xtmpa ;Lookup mul table of low nibble
  201. vpxorq xtmph2, xtmph2, xtmpl2 ;GF add high and low partials
  202. vpxorq xd2, xd2, xtmph2 ;xd2 += partial
  203. ; dest3
  204. vpshufb xtmph3 {k1}{z}, xgft3_hi, x0 ;Lookup mul table of high nibble
  205. vpshufb xtmpl3 {k1}{z}, xgft3_lo, xtmpa ;Lookup mul table of low nibble
  206. vpxorq xtmph3, xtmph3, xtmpl3 ;GF add high and low partials
  207. vpxorq xd3, xd3, xtmph3 ;xd2 += partial
  208. ; dest4
  209. vpshufb xtmph4 {k1}{z}, xgft4_hi, x0 ;Lookup mul table of high nibble
  210. vpshufb xtmpl4 {k1}{z}, xgft4_lo, xtmpa ;Lookup mul table of low nibble
  211. vpxorq xtmph4, xtmph4, xtmpl4 ;GF add high and low partials
  212. vpxorq xd4, xd4, xtmph4 ;xd2 += partial
  213. XSTR [dest1+pos], xd1
  214. XSTR [dest2+pos], xd2
  215. XSTR [dest3+pos], xd3
  216. XSTR [dest4+pos], xd4
  217. add pos, 64 ;Loop on 64 bytes at a time
  218. cmp pos, len
  219. jle .loop64
  220. lea tmp, [len + 64]
  221. cmp pos, tmp
  222. je .return_pass
  223. ;; Tail len
  224. mov pos, (1 << 63)
  225. lea tmp, [len + 64 - 1]
  226. and tmp, 63
  227. sarx pos, pos, tmp
  228. kmovq k1, pos
  229. mov pos, len ;Overlapped offset length-64
  230. jmp .loop64 ;Do one more overlap pass
  231. .return_pass:
  232. mov return, 0
  233. FUNC_RESTORE
  234. ret
  235. .return_fail:
  236. mov return, 1
  237. FUNC_RESTORE
  238. ret
  239. endproc_frame
  240. %else
  241. %ifidn __OUTPUT_FORMAT__, win64
  242. global no_gf_4vect_mad_avx512
  243. no_gf_4vect_mad_avx512:
  244. %endif
  245. %endif ; ifdef HAVE_AS_KNOWS_AVX512