gf_2vect_mad_avx512.asm 6.3 KB

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  1. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  2. ; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
  3. ;
  4. ; Redistribution and use in source and binary forms, with or without
  5. ; modification, are permitted provided that the following conditions
  6. ; are met:
  7. ; * Redistributions of source code must retain the above copyright
  8. ; notice, this list of conditions and the following disclaimer.
  9. ; * Redistributions in binary form must reproduce the above copyright
  10. ; notice, this list of conditions and the following disclaimer in
  11. ; the documentation and/or other materials provided with the
  12. ; distribution.
  13. ; * Neither the name of Intel Corporation nor the names of its
  14. ; contributors may be used to endorse or promote products derived
  15. ; from this software without specific prior written permission.
  16. ;
  17. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20. ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21. ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22. ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23. ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24. ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25. ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26. ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29. ;;;
  30. ;;; gf_2vect_mad_avx512(len, vec, vec_i, mul_array, src, dest);
  31. ;;;
  32. %include "reg_sizes.asm"
  33. %ifdef HAVE_AS_KNOWS_AVX512
  34. %ifidn __OUTPUT_FORMAT__, elf64
  35. %define arg0 rdi
  36. %define arg1 rsi
  37. %define arg2 rdx
  38. %define arg3 rcx
  39. %define arg4 r8
  40. %define arg5 r9
  41. %define tmp r11
  42. %define tmp2 r10
  43. %define return rax
  44. %define func(x) x:
  45. %define FUNC_SAVE
  46. %define FUNC_RESTORE
  47. %endif
  48. %ifidn __OUTPUT_FORMAT__, win64
  49. %define arg0 rcx
  50. %define arg1 rdx
  51. %define arg2 r8
  52. %define arg3 r9
  53. %define arg4 r12
  54. %define arg5 r15
  55. %define tmp r11
  56. %define tmp2 r10
  57. %define return rax
  58. %define stack_size 16*9 + 3*8 ; must be an odd multiple of 8
  59. %define arg(x) [rsp + stack_size + PS + PS*x]
  60. %define func(x) proc_frame x
  61. %macro FUNC_SAVE 0
  62. sub rsp, stack_size
  63. vmovdqa [rsp+16*0],xmm6
  64. vmovdqa [rsp+16*1],xmm7
  65. vmovdqa [rsp+16*2],xmm8
  66. vmovdqa [rsp+16*3],xmm9
  67. vmovdqa [rsp+16*4],xmm10
  68. vmovdqa [rsp+16*5],xmm11
  69. vmovdqa [rsp+16*6],xmm12
  70. vmovdqa [rsp+16*7],xmm13
  71. vmovdqa [rsp+16*8],xmm14
  72. save_reg r12, 9*16 + 0*8
  73. save_reg r15, 9*16 + 1*8
  74. end_prolog
  75. mov arg4, arg(4)
  76. mov arg5, arg(5)
  77. %endmacro
  78. %macro FUNC_RESTORE 0
  79. vmovdqa xmm6, [rsp+16*0]
  80. vmovdqa xmm7, [rsp+16*1]
  81. vmovdqa xmm8, [rsp+16*2]
  82. vmovdqa xmm9, [rsp+16*3]
  83. vmovdqa xmm10, [rsp+16*4]
  84. vmovdqa xmm11, [rsp+16*5]
  85. vmovdqa xmm12, [rsp+16*6]
  86. vmovdqa xmm13, [rsp+16*7]
  87. vmovdqa xmm14, [rsp+16*8]
  88. mov r12, [rsp + 9*16 + 0*8]
  89. mov r15, [rsp + 9*16 + 1*8]
  90. add rsp, stack_size
  91. %endmacro
  92. %endif
  93. %define PS 8
  94. %define len arg0
  95. %define len.w arg0.w
  96. %define vec arg1
  97. %define vec_i arg2
  98. %define mul_array arg3
  99. %define src arg4
  100. %define dest1 arg5
  101. %define pos return
  102. %define pos.w return.w
  103. %define dest2 tmp2
  104. %ifndef EC_ALIGNED_ADDR
  105. ;;; Use Un-aligned load/store
  106. %define XLDR vmovdqu8
  107. %define XSTR vmovdqu8
  108. %else
  109. ;;; Use Non-temporal load/stor
  110. %ifdef NO_NT_LDST
  111. %define XLDR vmovdqa
  112. %define XSTR vmovdqa
  113. %else
  114. %define XLDR vmovntdqa
  115. %define XSTR vmovntdq
  116. %endif
  117. %endif
  118. default rel
  119. [bits 64]
  120. section .text
  121. %define x0 zmm0
  122. %define xtmpa zmm1
  123. %define xtmph1 zmm2
  124. %define xtmpl1 zmm3
  125. %define xtmph2 zmm4
  126. %define xtmpl2 zmm5
  127. %define xd1 zmm6
  128. %define xd2 zmm7
  129. %define xtmpd1 zmm8
  130. %define xtmpd2 zmm9
  131. %define xgft1_hi zmm10
  132. %define xgft1_lo zmm11
  133. %define xgft1_loy ymm11
  134. %define xgft2_hi zmm12
  135. %define xgft2_lo zmm13
  136. %define xgft2_loy ymm13
  137. %define xmask0f zmm14
  138. align 16
  139. global gf_2vect_mad_avx512:ISAL_SYM_TYPE_FUNCTION
  140. func(gf_2vect_mad_avx512)
  141. %ifidn __OUTPUT_FORMAT__, macho64
  142. global _gf_2vect_mad_avx512:ISAL_SYM_TYPE_FUNCTION
  143. func(_gf_2vect_mad_avx512)
  144. %endif
  145. FUNC_SAVE
  146. sub len, 64
  147. jl .return_fail
  148. xor pos, pos
  149. mov tmp, 0x0f
  150. vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
  151. sal vec_i, 5 ;Multiply by 32
  152. sal vec, 5
  153. lea tmp, [mul_array + vec_i]
  154. vmovdqu xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
  155. vmovdqu xgft2_loy, [tmp+vec] ;Load array Bx{00}..{0f}, Bx{00}..{f0}
  156. vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x55
  157. vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x00
  158. vshufi64x2 xgft2_hi, xgft2_lo, xgft2_lo, 0x55
  159. vshufi64x2 xgft2_lo, xgft2_lo, xgft2_lo, 0x00
  160. mov dest2, [dest1+PS] ; reuse mul_array
  161. mov dest1, [dest1]
  162. mov tmp, -1
  163. kmovq k1, tmp
  164. .loop64:
  165. XLDR xd1, [dest1+pos] ;Get next dest vector
  166. XLDR xd2, [dest2+pos] ;Get next dest vector
  167. XLDR x0, [src+pos] ;Get next source vector
  168. vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
  169. vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
  170. vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
  171. vpshufb xtmph1 {k1}{z}, xgft1_hi, x0 ;Lookup mul table of high nibble
  172. vpshufb xtmpl1 {k1}{z}, xgft1_lo, xtmpa ;Lookup mul table of low nibble
  173. vpxorq xtmph1, xtmph1, xtmpl1 ;GF add high and low partials
  174. vpxorq xd1, xd1, xtmph1 ;xd1 += partial
  175. vpshufb xtmph2 {k1}{z}, xgft2_hi, x0 ;Lookup mul table of high nibble
  176. vpshufb xtmpl2 {k1}{z}, xgft2_lo, xtmpa ;Lookup mul table of low nibble
  177. vpxorq xtmph2, xtmph2, xtmpl2 ;GF add high and low partials
  178. vpxorq xd2, xd2, xtmph2 ;xd2 += partial
  179. XSTR [dest1+pos], xd1
  180. XSTR [dest2+pos], xd2
  181. add pos, 64 ;Loop on 64 bytes at a time
  182. cmp pos, len
  183. jle .loop64
  184. lea tmp, [len + 64]
  185. cmp pos, tmp
  186. je .return_pass
  187. ;; Tail len
  188. mov pos, (1 << 63)
  189. lea tmp, [len + 64 - 1]
  190. and tmp, 63
  191. sarx pos, pos, tmp
  192. kmovq k1, pos
  193. mov pos, len ;Overlapped offset length-64
  194. jmp .loop64 ;Do one more overlap pass
  195. .return_pass:
  196. mov return, 0
  197. FUNC_RESTORE
  198. ret
  199. .return_fail:
  200. mov return, 1
  201. FUNC_RESTORE
  202. ret
  203. endproc_frame
  204. %else
  205. %ifidn __OUTPUT_FORMAT__, win64
  206. global no_gf_2vect_mad_avx512
  207. no_gf_2vect_mad_avx512:
  208. %endif
  209. %endif ; ifdef HAVE_AS_KNOWS_AVX512