turbob64sse.c 20 KB

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  1. /**
  2. Copyright (c) 2016-2019, Powturbo
  3. All rights reserved.
  4. Redistribution and use in source and binary forms, with or without
  5. modification, are permitted provided that the following conditions are
  6. met:
  7. 1. Redistributions of source code must retain the above copyright
  8. notice, this list of conditions and the following disclaimer.
  9. 2. Redistributions in binary form must reproduce the above copyright
  10. notice, this list of conditions and the following disclaimer in the
  11. documentation and/or other materials provided with the distribution.
  12. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  13. IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  14. TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  15. PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  16. HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  17. SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  18. TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  19. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  20. LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  21. NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  22. SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23. - homepage : https://sites.google.com/site/powturbo/
  24. - github : https://github.com/powturbo
  25. - twitter : https://twitter.com/powturbo
  26. - email : powturbo [_AT_] gmail [_DOT_] com
  27. **/
  28. // TubeBase64: ssse3 + arm neon functions (see also turbob64avx2)
  29. #include <string.h>
  30. #if defined(__AVX__)
  31. #include <immintrin.h>
  32. #define FUNPREF tb64avx
  33. #elif defined(__SSE4_1__)
  34. #include <smmintrin.h>
  35. #define FUNPREF tb64sse
  36. #elif defined(__SSSE3__)
  37. #ifdef __powerpc64__
  38. #define __SSE__ 1
  39. #define __SSE2__ 1
  40. #define __SSE3__ 1
  41. #define NO_WARN_X86_INTRINSICS 1
  42. #endif
  43. #define FUNPREF tb64sse
  44. #include <tmmintrin.h>
  45. #elif defined(__SSE2__)
  46. #include <emmintrin.h>
  47. #elif defined(__ARM_NEON)
  48. #include <arm_neon.h>
  49. #endif
  50. #define UA_MEMCPY
  51. #include "conf.h"
  52. #include "turbob64.h"
  53. #include "turbob64_.h"
  54. #ifdef __ARM_NEON //----------------------------------- arm neon --------------------------------
  55. #define _ 0xff // invald entry
  56. static const unsigned char lut[] = {
  57. _, _, _, _, _, _, _, _, _, _, _, _, _, _, _, _,
  58. _, _, _, _, _, _, _, _, _, _, _, _, _, _, _, _,
  59. _, _, _, _, _, _, _, _, _, _, _,62, _, _, _,63,
  60. 52,53,54,55,56,57,58,59,60,61, _, _, _, _, _, _,
  61. _, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,
  62. 15,16,17,18,19,20,21,22,23,24,25, _, _, _, _, _,
  63. _,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,
  64. 41,42,43,44,45,46,47,48,49,50,51, _, _, _, _, _,
  65. };
  66. #undef _
  67. #ifndef vld1q_u8_x4
  68. static inline uint8x16x4_t vld1q_u8_x4(const uint8_t *lut) {
  69. uint8x16x4_t v;
  70. v.val[0] = vld1q_u8(lut);
  71. v.val[1] = vld1q_u8(lut+16);
  72. v.val[2] = vld1q_u8(lut+32);
  73. v.val[3] = vld1q_u8(lut+48);
  74. return v;
  75. }
  76. #endif
  77. #define B64D(iv, ov) {\
  78. iv.val[0] = vqtbx4q_u8(vqtbl4q_u8(vlut1, veorq_u8(iv.val[0], cv40)), vlut0, iv.val[0]);\
  79. iv.val[1] = vqtbx4q_u8(vqtbl4q_u8(vlut1, veorq_u8(iv.val[1], cv40)), vlut0, iv.val[1]);\
  80. iv.val[2] = vqtbx4q_u8(vqtbl4q_u8(vlut1, veorq_u8(iv.val[2], cv40)), vlut0, iv.val[2]);\
  81. iv.val[3] = vqtbx4q_u8(vqtbl4q_u8(vlut1, veorq_u8(iv.val[3], cv40)), vlut0, iv.val[3]);\
  82. \
  83. ov.val[0] = vorrq_u8(vshlq_n_u8(iv.val[0], 2), vshrq_n_u8(iv.val[1], 4));\
  84. ov.val[1] = vorrq_u8(vshlq_n_u8(iv.val[1], 4), vshrq_n_u8(iv.val[2], 2));\
  85. ov.val[2] = vorrq_u8(vshlq_n_u8(iv.val[2], 6), iv.val[3] );\
  86. }
  87. #define _MM_B64CHK(iv, xv) xv = vorrq_u8(xv, vorrq_u8(vorrq_u8(iv.val[0], iv.val[1]), vorrq_u8(iv.val[2], iv.val[3])))
  88. size_t tb64ssedec(const unsigned char *in, size_t inlen, unsigned char *out) {
  89. const unsigned char *ip;
  90. unsigned char *op;
  91. const uint8x16x4_t vlut0 = vld1q_u8_x4( lut),
  92. vlut1 = vld1q_u8_x4(&lut[64]);
  93. const uint8x16_t cv40 = vdupq_n_u8(0x40);
  94. uint8x16_t xv = vdupq_n_u8(0);
  95. #define ND 256
  96. for(ip = in, op = out; ip != in+(inlen&~(ND-1)); ip += ND, op += (ND/4)*3) { PREFETCH(ip,256,0);
  97. uint8x16x4_t iv0 = vld4q_u8(ip),
  98. iv1 = vld4q_u8(ip+64);
  99. uint8x16x3_t ov0,ov1;
  100. B64D(iv0, ov0);
  101. #if ND > 128
  102. CHECK1(_MM_B64CHK(iv0,xv));
  103. #else
  104. CHECK0(_MM_B64CHK(iv0,xv));
  105. #endif
  106. B64D(iv1, ov1); CHECK1(_MM_B64CHK(iv1,xv));
  107. #if ND > 128
  108. iv0 = vld4q_u8(ip+128);
  109. iv1 = vld4q_u8(ip+192);
  110. #endif
  111. vst3q_u8(op, ov0);
  112. vst3q_u8(op+48, ov1);
  113. #if ND > 128
  114. B64D(iv0,ov0); CHECK1(_MM_B64CHK(iv0,xv));
  115. B64D(iv1,ov1);
  116. vst3q_u8(op+ 96, ov0);
  117. vst3q_u8(op+144, ov1);
  118. CHECK0(_MM_B64CHK(iv1,xv));
  119. #endif
  120. }
  121. for( ; ip != in+(inlen&~(64-1)); ip += 64, op += (64/4)*3) {
  122. uint8x16x4_t iv = vld4q_u8(ip);
  123. uint8x16x3_t ov; B64D(iv,ov);
  124. vst3q_u8(op, ov);
  125. CHECK0(xv = vorrq_u8(xv, vorrq_u8(vorrq_u8(iv.val[0], iv.val[1]), vorrq_u8(iv.val[2], iv.val[3]))));
  126. }
  127. size_t rc;
  128. if(!(rc=tb64xdec(ip, inlen&(64-1), op)) || vaddvq_u8(vshrq_n_u8(xv,7))) return 0; //decode all
  129. return (op-out)+rc;
  130. }
  131. //--------------------------------------------------------------------------------------------------
  132. #define B64E(iv, ov) {\
  133. ov.val[0] = vshrq_n_u8(iv.val[0], 2);\
  134. ov.val[1] = vandq_u8(vorrq_u8(vshlq_n_u8(iv.val[0], 4), vshrq_n_u8(iv.val[1], 4)), cv3f);\
  135. ov.val[2] = vandq_u8(vorrq_u8(vshlq_n_u8(iv.val[1], 2), vshrq_n_u8(iv.val[2], 6)), cv3f);\
  136. ov.val[3] = vandq_u8( iv.val[2], cv3f);\
  137. \
  138. ov.val[0] = vqtbl4q_u8(vlut, ov.val[0]);\
  139. ov.val[1] = vqtbl4q_u8(vlut, ov.val[1]);\
  140. ov.val[2] = vqtbl4q_u8(vlut, ov.val[2]);\
  141. ov.val[3] = vqtbl4q_u8(vlut, ov.val[3]);\
  142. }
  143. size_t tb64sseenc(const unsigned char* in, size_t inlen, unsigned char *out) {
  144. static unsigned char lut[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
  145. const unsigned char *ip;
  146. unsigned char *op;
  147. const size_t outlen = TB64ENCLEN(inlen);
  148. const uint8x16x4_t vlut = vld1q_u8_x4(lut);
  149. const uint8x16_t cv3f = vdupq_n_u8(0x3f);
  150. #define NE 128 // 256//
  151. for(ip = in, op = out; op != out+(outlen&~(NE-1)); op += NE, ip += (NE/4)*3) {
  152. uint8x16x3_t iv0 = vld3q_u8(ip),
  153. iv1 = vld3q_u8(ip+48);
  154. uint8x16x4_t ov0,ov1; B64E(iv0, ov0); B64E(iv1, ov1);
  155. #if NE > 128
  156. iv0 = vld3q_u8(ip+ 96);
  157. iv1 = vld3q_u8(ip+144);
  158. #endif
  159. vst4q_u8(op, ov0);
  160. vst4q_u8(op+64, ov1); //PREFETCH(ip,256,0);
  161. #if NE > 128
  162. B64E(iv0, ov0); B64E(iv1, ov1);
  163. vst4q_u8(op+128, ov0);
  164. vst4q_u8(op+192, ov1);
  165. #endif
  166. }
  167. for( ; op != out+(outlen&~(64-1)); op += 64, ip += (64/4)*3) {
  168. const uint8x16x3_t iv = vld3q_u8(ip);
  169. uint8x16x4_t ov;
  170. B64E(iv, ov);
  171. vst4q_u8(op,ov);
  172. }
  173. EXTAIL();
  174. return outlen;
  175. }
  176. #elif defined(__SSSE3__) //----------------- SSSE3 / SSE4.1 / AVX (derived from the AVX2 functions ) -----------------------------------------------------------------
  177. #define OVD 4
  178. size_t TEMPLATE2(FUNPREF, dec)(const unsigned char *in, size_t inlen, unsigned char *out) {
  179. if(inlen >= 16+OVD) {
  180. const unsigned char *ip;
  181. unsigned char *op;
  182. #ifdef __AVX__
  183. #define ND 64
  184. #else
  185. #define ND 32
  186. #endif
  187. __m128i vx = _mm_setzero_si128();
  188. const __m128i delta_asso = _mm_setr_epi8(0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f);
  189. const __m128i delta_values = _mm_setr_epi8(0x00, 0x00, 0x00, 0x13, 0x04, 0xbf, 0xbf, 0xb9, 0xb9, 0x00, 0x10, 0xc3, 0xbf, 0xbf, 0xb9, 0xb9);
  190. #ifndef NB64CHECK
  191. const __m128i check_asso = _mm_setr_epi8(0x0d, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x03, 0x07, 0x0b, 0x0b, 0x0b, 0x0f);
  192. const __m128i check_values = _mm_setr_epi8(0x80, 0x80, 0x80, 0x80, 0xcf, 0xbf, 0xd5, 0xa6, 0xb5, 0x86, 0xd1, 0x80, 0xb1, 0x80, 0x91, 0x80);
  193. #endif
  194. const __m128i cpv = _mm_set_epi8( -1, -1, -1, -1, 12, 13, 14, 8, 9, 10, 4, 5, 6, 0, 1, 2);
  195. for(ip = in, op = out; ip < (in+inlen)-(ND+OVD); ip += ND, op += (ND/4)*3) {
  196. __m128i iv0 = _mm_loadu_si128((__m128i *) ip),
  197. iv1 = _mm_loadu_si128((__m128i *)(ip+16));
  198. __m128i ov0,shifted0; MM_MAP8TO6(iv0, shifted0,delta_asso, delta_values, ov0); MM_PACK8TO6(ov0, cpv);
  199. __m128i ov1,shifted1; MM_MAP8TO6(iv1, shifted1,delta_asso, delta_values, ov1); MM_PACK8TO6(ov1, cpv);
  200. _mm_storeu_si128((__m128i*) op, ov0);
  201. _mm_storeu_si128((__m128i*)(op+12), ov1); PREFETCH(ip,1024,0);
  202. #if ND > 32
  203. __m128i iv2 = _mm_loadu_si128((__m128i *)(ip+32)),
  204. iv3 = _mm_loadu_si128((__m128i *)(ip+48));
  205. #endif
  206. CHECK0(MM_B64CHK(iv0, shifted0, check_asso, check_values, vx));
  207. CHECK1(MM_B64CHK(iv1, shifted1, check_asso, check_values, vx));
  208. #if ND > 32
  209. __m128i ov2,shifted2; MM_MAP8TO6(iv2, shifted2,delta_asso, delta_values, ov2); MM_PACK8TO6(ov2, cpv);
  210. __m128i ov3,shifted3; MM_MAP8TO6(iv3, shifted3,delta_asso, delta_values, ov3); MM_PACK8TO6(ov3, cpv);
  211. _mm_storeu_si128((__m128i*)(op+24), ov2);
  212. _mm_storeu_si128((__m128i*)(op+36), ov3);
  213. CHECK1(MM_B64CHK(iv2, shifted2, check_asso, check_values, vx));
  214. CHECK1(MM_B64CHK(iv3, shifted3, check_asso, check_values, vx));
  215. #endif
  216. }
  217. #ifdef __AVX__
  218. for(; ip < (in+inlen)-(16+OVD); ip += 16, op += (16/4)*3) {
  219. #else
  220. if(ip < (in+inlen)-(16+OVD)) {
  221. #endif
  222. __m128i iv0 = _mm_loadu_si128((__m128i *) ip);
  223. __m128i ov0, shifted0; MM_MAP8TO6(iv0, shifted0,delta_asso, delta_values, ov0); MM_PACK8TO6(ov0, cpv);
  224. _mm_storeu_si128((__m128i*) op, ov0);
  225. CHECK1(MM_B64CHK(iv0, shifted0, check_asso, check_values, vx));
  226. #ifndef __AVX__
  227. ip += 16; op += (16/4)*3;
  228. #endif
  229. }
  230. size_t rc;
  231. if(!(rc = _tb64xdec(ip, inlen-(ip-in), op)) || _mm_movemask_epi8(vx)) return 0;
  232. return (op-out)+rc;
  233. }
  234. return _tb64xdec(in, inlen, out);
  235. }
  236. #define OVE 8
  237. size_t TEMPLATE2(FUNPREF, enc)(const unsigned char* in, size_t inlen, unsigned char *out) {
  238. const unsigned char *ip = in;
  239. unsigned char *op = out;
  240. size_t outlen = TB64ENCLEN(inlen);
  241. #ifdef __AVX__
  242. #define NE 64
  243. #else
  244. #define NE 32
  245. #endif
  246. if(outlen >= 16+OVE) {
  247. const __m128i shuf = _mm_set_epi8(10,11, 9, 10, 7, 8, 6, 7, 4, 5, 3, 4, 1, 2, 0, 1);
  248. for(; op <= (out+outlen)-(NE+OVE); op += NE, ip += (NE/4)*3) { PREFETCH(ip,1024,0);
  249. __m128i v0 = _mm_loadu_si128((__m128i*)ip),
  250. v1 = _mm_loadu_si128((__m128i*)(ip+12));
  251. #if NE > 32
  252. __m128i v2 = _mm_loadu_si128((__m128i*)(ip+24)),
  253. v3 = _mm_loadu_si128((__m128i*)(ip+36));
  254. #endif
  255. v0 = _mm_shuffle_epi8(v0, shuf);
  256. v1 = _mm_shuffle_epi8(v1, shuf);
  257. v0 = mm_unpack6to8(v0);
  258. v1 = mm_unpack6to8(v1);
  259. v0 = mm_map6to8(v0);
  260. v1 = mm_map6to8(v1);
  261. _mm_storeu_si128((__m128i*) op, v0);
  262. _mm_storeu_si128((__m128i*)(op+16), v1);
  263. #if NE > 32
  264. v2 = _mm_shuffle_epi8(v2, shuf);
  265. v3 = _mm_shuffle_epi8(v3, shuf);
  266. v2 = mm_unpack6to8(v2);
  267. v3 = mm_unpack6to8(v3);
  268. v2 = mm_map6to8(v2);
  269. v3 = mm_map6to8(v3);
  270. _mm_storeu_si128((__m128i*)(op+32), v2);
  271. _mm_storeu_si128((__m128i*)(op+48), v3);
  272. #endif
  273. }
  274. for(; op <= (out+outlen)-(16+OVE); op += 16, ip += (16/4)*3) {
  275. __m128i v0 = _mm_loadu_si128((__m128i*)ip);
  276. v0 = _mm_shuffle_epi8(v0, shuf);
  277. v0 = mm_unpack6to8(v0);
  278. v0 = mm_map6to8(v0);
  279. _mm_storeu_si128((__m128i*) op, v0);
  280. }
  281. }
  282. EXTAIL();
  283. return outlen;
  284. }
  285. #endif
  286. //-------------------------------------------------------------------------------------------------------------------
  287. #if !defined(__AVX__) //include only 1 time
  288. size_t tb64memcpy(const unsigned char* in, size_t inlen, unsigned char *out) {
  289. memcpy(out, in, inlen);
  290. return inlen;
  291. }
  292. static unsigned _cpuisa;
  293. //--------------------- CPU detection -------------------------------------------
  294. #if defined(__i386__) || defined(__x86_64__)
  295. #if _MSC_VER >=1300
  296. #include <intrin.h>
  297. #elif defined (__INTEL_COMPILER)
  298. #include <x86intrin.h>
  299. #endif
  300. static inline void cpuid(int reg[4], int id) {
  301. #if defined (_MSC_VER) //|| defined (__INTEL_COMPILER)
  302. __cpuidex(reg, id, 0);
  303. #elif defined(__i386__) || defined(__x86_64__)
  304. __asm("cpuid" : "=a"(reg[0]),"=b"(reg[1]),"=c"(reg[2]),"=d"(reg[3]) : "a"(id),"c"(0) : );
  305. #endif
  306. }
  307. static inline uint64_t xgetbv (int ctr) {
  308. #if(defined _MSC_VER && (_MSC_FULL_VER >= 160040219) || defined __INTEL_COMPILER)
  309. return _xgetbv(ctr);
  310. #elif defined(__i386__) || defined(__x86_64__)
  311. unsigned a, d;
  312. __asm("xgetbv" : "=a"(a),"=d"(d) : "c"(ctr) : );
  313. return (uint64_t)d << 32 | a;
  314. #else
  315. unsigned a=0, d=0;
  316. return (uint64_t)d << 32 | a;
  317. #endif
  318. }
  319. #endif
  320. #define AVX512F 0x001
  321. #define AVX512DQ 0x002
  322. #define AVX512IFMA 0x004
  323. #define AVX512PF 0x008
  324. #define AVX512ER 0x010
  325. #define AVX512CD 0x020
  326. #define AVX512BW 0x040
  327. #define AVX512VL 0x080
  328. #define AVX512VNNI 0x100
  329. #define AVX512VBMI 0x200
  330. #define AVX512VBMI2 0x400
  331. #define IS_SSE 0x10
  332. #define IS_SSE2 0x20
  333. #define IS_SSE3 0x30
  334. #define IS_SSSE3 0x32
  335. #define IS_POWER9 0x34 // powerpc
  336. #define IS_NEON 0x38 // arm neon
  337. #define IS_SSE41 0x40
  338. #define IS_SSE41x 0x41 //+popcount
  339. #define IS_SSE42 0x42
  340. #define IS_AVX 0x50
  341. #define IS_AVX2 0x60
  342. #define IS_AVX512 0x800
  343. unsigned cpuisa(void) {
  344. int c[4] = {0};
  345. if(_cpuisa) return _cpuisa;
  346. _cpuisa++;
  347. #if defined(__i386__) || defined(__x86_64__)
  348. cpuid(c, 0);
  349. if(c[0]) {
  350. cpuid(c, 1);
  351. //family = ((c >> 8) & 0xf) + ((c >> 20) & 0xff)
  352. //model = ((c >> 4) & 0xf) + ((c >> 12) & 0xf0)
  353. if( c[3] & (1 << 25)) { _cpuisa = IS_SSE;
  354. if( c[3] & (1 << 26)) { _cpuisa = IS_SSE2;
  355. if( c[2] & (1 << 0)) { _cpuisa = IS_SSE3;
  356. // _cpuisa = IS_SSE3SLOW; // Atom SSSE3 slow
  357. if( c[2] & (1 << 9)) { _cpuisa = IS_SSSE3;
  358. if( c[2] & (1 << 19)) { _cpuisa = IS_SSE41;
  359. if( c[2] & (1 << 23)) { _cpuisa = IS_SSE41x; // +popcount
  360. if( c[2] & (1 << 20)) { _cpuisa = IS_SSE42; // SSE4.2
  361. if((c[2] & (1 << 28)) &&
  362. (c[2] & (1 << 27)) && // OSXSAVE
  363. (c[2] & (1 << 26)) && // XSAVE
  364. (xgetbv(0) & 6)==6) { _cpuisa = IS_AVX; // AVX
  365. if(c[2]& (1 << 3)) _cpuisa |= 1; // +FMA3
  366. if(c[2]& (1 << 16)) _cpuisa |= 2; // +FMA4
  367. if(c[2]& (1 << 25)) _cpuisa |= 4; // +AES
  368. cpuid(c, 7);
  369. if(c[1] & (1 << 5)) { _cpuisa = IS_AVX2;
  370. if(c[1] & (1 << 16)) {
  371. cpuid(c, 0xd);
  372. if((c[0] & 0x60)==0x60) { _cpuisa = IS_AVX512;
  373. cpuid(c, 7);
  374. if(c[1] & (1<<16)) _cpuisa |= AVX512F;
  375. if(c[1] & (1<<17)) _cpuisa |= AVX512DQ;
  376. if(c[1] & (1<<21)) _cpuisa |= AVX512IFMA;
  377. if(c[1] & (1<<26)) _cpuisa |= AVX512PF;
  378. if(c[1] & (1<<27)) _cpuisa |= AVX512ER;
  379. if(c[1] & (1<<28)) _cpuisa |= AVX512CD;
  380. if(c[1] & (1<<30)) _cpuisa |= AVX512BW;
  381. if(c[1] & (1u<<31)) _cpuisa |= AVX512VL;
  382. if(c[2] & (1<< 1)) _cpuisa |= AVX512VBMI;
  383. if(c[2] & (1<<11)) _cpuisa |= AVX512VNNI;
  384. if(c[2] & (1<< 6)) _cpuisa |= AVX512VBMI2;
  385. }}}
  386. }}}}}}}}}
  387. #elif defined(__powerpc64__)
  388. _cpuisa = IS_POWER9; // power9
  389. #elif defined(__ARM_NEON)
  390. _cpuisa = IS_NEON; // ARM_NEON
  391. #endif
  392. return _cpuisa;
  393. }
  394. unsigned cpuini(unsigned cpuisa) { if(cpuisa) _cpuisa = cpuisa; return _cpuisa; }
  395. char *cpustr(unsigned cpuisa) {
  396. if(!cpuisa) cpuisa = _cpuisa;
  397. #if defined(__i386__) || defined(__x86_64__)
  398. if(cpuisa >= IS_AVX512) {
  399. if(cpuisa & AVX512VBMI2) return "avx512vbmi2";
  400. if(cpuisa & AVX512VBMI) return "avx512vbmi";
  401. if(cpuisa & AVX512VNNI) return "avx512vnni";
  402. if(cpuisa & AVX512VL) return "avx512vl";
  403. if(cpuisa & AVX512BW) return "avx512bw";
  404. if(cpuisa & AVX512CD) return "avx512cd";
  405. if(cpuisa & AVX512ER) return "avx512er";
  406. if(cpuisa & AVX512PF) return "avx512pf";
  407. if(cpuisa & AVX512IFMA) return "avx512ifma";
  408. if(cpuisa & AVX512DQ) return "avx512dq";
  409. if(cpuisa & AVX512F) return "avx512f";
  410. return "avx512";
  411. }
  412. else if(cpuisa >= IS_AVX2) return "avx2";
  413. else if(cpuisa >= IS_AVX)
  414. switch(cpuisa&0xf) {
  415. case 1: return "avx+fma3";
  416. case 2: return "avx+fma4";
  417. case 4: return "avx+aes";
  418. case 5: return "avx+fma3+aes";
  419. default:return "avx";
  420. }
  421. else if(cpuisa >= IS_SSE42) return "sse4.2";
  422. else if(cpuisa >= IS_SSE41x) return "sse4.1+popcnt";
  423. else if(cpuisa >= IS_SSE41) return "sse4.1";
  424. else if(cpuisa >= IS_SSSE3) return "ssse3";
  425. else if(cpuisa >= IS_SSE3) return "sse3";
  426. else if(cpuisa >= IS_SSE2) return "sse2";
  427. else if(cpuisa >= IS_SSE) return "sse";
  428. #elif defined(__powerpc64__)
  429. if(cpuisa >= IS_POWER9) return "power9";
  430. #elif defined(__ARM_NEON)
  431. if(cpuisa >= IS_NEON) return "arm_neon";
  432. #endif
  433. return "none";
  434. }
  435. //---------------------------------------------------------------------------------
  436. TB64FUNC _tb64e = tb64xenc;
  437. TB64FUNC _tb64d = tb64xdec;
  438. static int tb64set;
  439. void tb64ini(unsigned id, unsigned isshort) {
  440. int i;
  441. if(tb64set) return;
  442. tb64set++;
  443. i = id?id:cpuisa();
  444. #if defined(__i386__) || defined(__x86_64__)
  445. #ifdef USE_AVX512
  446. if(i >= IS_AVX512) {
  447. _tb64e = i >= (IS_AVX512|AVX512VL)?tb64avx2enc:tb64avx2enc;
  448. _tb64d = tb64avx512dec;
  449. } else
  450. #endif
  451. #ifndef NO_AVX2
  452. if(i >= IS_AVX2) {
  453. _tb64e = isshort?_tb64avx2enc:tb64avx2enc;
  454. _tb64d = isshort?_tb64avx2dec:tb64avx2dec;
  455. } else
  456. #endif
  457. #ifndef NO_AVX
  458. if(i >= IS_AVX) {
  459. _tb64e = tb64avxenc;
  460. _tb64d = tb64avxdec;
  461. } else
  462. #endif
  463. #endif
  464. #if defined(__i386__) || defined(__x86_64__) || defined(__ARM_NEON) || defined(__powerpc64__)
  465. #ifndef NO_SSE
  466. if(i >= IS_SSSE3) {
  467. _tb64e = tb64sseenc;
  468. _tb64d = tb64ssedec;
  469. }
  470. #endif
  471. #endif
  472. }
  473. size_t tb64enc(const unsigned char *in, size_t inlen, unsigned char *out) {
  474. if(!tb64set) tb64ini(0,0);
  475. return _tb64e(in,inlen,out);
  476. }
  477. size_t tb64dec(const unsigned char *in, size_t inlen, unsigned char *out) {
  478. if(!tb64set) tb64ini(0,0);
  479. return _tb64d(in,inlen,out);
  480. }
  481. #endif