gf_vect_mad_sse.asm 5.2 KB

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  1. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  2. ; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
  3. ;
  4. ; Redistribution and use in source and binary forms, with or without
  5. ; modification, are permitted provided that the following conditions
  6. ; are met:
  7. ; * Redistributions of source code must retain the above copyright
  8. ; notice, this list of conditions and the following disclaimer.
  9. ; * Redistributions in binary form must reproduce the above copyright
  10. ; notice, this list of conditions and the following disclaimer in
  11. ; the documentation and/or other materials provided with the
  12. ; distribution.
  13. ; * Neither the name of Intel Corporation nor the names of its
  14. ; contributors may be used to endorse or promote products derived
  15. ; from this software without specific prior written permission.
  16. ;
  17. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20. ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21. ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22. ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23. ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24. ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25. ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26. ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29. ;;;
  30. ;;; gf_vect_mad_sse(len, vec, vec_i, mul_array, src, dest);
  31. ;;;
  32. %include "reg_sizes.asm"
  33. %ifidn __OUTPUT_FORMAT__, win64
  34. %define arg0 rcx
  35. %define arg0.w ecx
  36. %define arg1 rdx
  37. %define arg2 r8
  38. %define arg3 r9
  39. %define arg4 r12
  40. %define arg5 r15
  41. %define tmp r11
  42. %define return rax
  43. %define return.w eax
  44. %define PS 8
  45. %define stack_size 16*3 + 3*8
  46. %define arg(x) [rsp + stack_size + PS + PS*x]
  47. %define func(x) proc_frame x
  48. %macro FUNC_SAVE 0
  49. sub rsp, stack_size
  50. movdqa [rsp+16*0],xmm6
  51. movdqa [rsp+16*1],xmm7
  52. movdqa [rsp+16*2],xmm8
  53. save_reg r12, 3*16 + 0*8
  54. save_reg r15, 3*16 + 1*8
  55. end_prolog
  56. mov arg4, arg(4)
  57. mov arg5, arg(5)
  58. %endmacro
  59. %macro FUNC_RESTORE 0
  60. movdqa xmm6, [rsp+16*0]
  61. movdqa xmm7, [rsp+16*1]
  62. movdqa xmm8, [rsp+16*2]
  63. mov r12, [rsp + 3*16 + 0*8]
  64. mov r15, [rsp + 3*16 + 1*8]
  65. add rsp, stack_size
  66. %endmacro
  67. %elifidn __OUTPUT_FORMAT__, elf64
  68. %define arg0 rdi
  69. %define arg0.w edi
  70. %define arg1 rsi
  71. %define arg2 rdx
  72. %define arg3 rcx
  73. %define arg4 r8
  74. %define arg5 r9
  75. %define tmp r11
  76. %define return rax
  77. %define return.w eax
  78. %define func(x) x:
  79. %define FUNC_SAVE
  80. %define FUNC_RESTORE
  81. %endif
  82. ;;; gf_vect_mad_sse(len, vec, vec_i, mul_array, src, dest)
  83. %define len arg0
  84. %define len.w arg0.w
  85. %define vec arg1
  86. %define vec_i arg2
  87. %define mul_array arg3
  88. %define src arg4
  89. %define dest arg5
  90. %define pos return
  91. %define pos.w return.w
  92. %ifndef EC_ALIGNED_ADDR
  93. ;;; Use Un-aligned load/store
  94. %define XLDR movdqu
  95. %define XSTR movdqu
  96. %else
  97. ;;; Use Non-temporal load/stor
  98. %ifdef NO_NT_LDST
  99. %define XLDR movdqa
  100. %define XSTR movdqa
  101. %else
  102. %define XLDR movntdqa
  103. %define XSTR movntdq
  104. %endif
  105. %endif
  106. default rel
  107. [bits 64]
  108. section .text
  109. %define xmask0f xmm8
  110. %define xgft_lo xmm7
  111. %define xgft_hi xmm6
  112. %define x0 xmm0
  113. %define xtmpa xmm1
  114. %define xtmph xmm2
  115. %define xtmpl xmm3
  116. %define xd xmm4
  117. %define xtmpd xmm5
  118. align 16
  119. global gf_vect_mad_sse:ISAL_SYM_TYPE_FUNCTION
  120. func(gf_vect_mad_sse)
  121. %ifidn __OUTPUT_FORMAT__, macho64
  122. global _gf_vect_mad_sse:ISAL_SYM_TYPE_FUNCTION
  123. func(_gf_vect_mad_sse)
  124. %endif
  125. FUNC_SAVE
  126. sub len, 16
  127. jl .return_fail
  128. xor pos, pos
  129. movdqa xmask0f, [mask0f] ;Load mask of lower nibble in each byte
  130. sal vec_i, 5 ;Multiply by 32
  131. movdqu xgft_lo, [vec_i+mul_array] ;Load array Cx{00}, Cx{01}, Cx{02}, ...
  132. movdqu xgft_hi, [vec_i+mul_array+16] ; " Cx{00}, Cx{10}, Cx{20}, ... , Cx{f0}
  133. XLDR xtmpd, [dest+len] ;backup the last 16 bytes in dest
  134. .loop16:
  135. XLDR xd, [dest+pos] ;Get next dest vector
  136. .loop16_overlap:
  137. XLDR x0, [src+pos] ;Get next source vector
  138. movdqa xtmph, xgft_hi ;Reload const array registers
  139. movdqa xtmpl, xgft_lo
  140. movdqa xtmpa, x0 ;Keep unshifted copy of src
  141. psraw x0, 4 ;Shift to put high nibble into bits 4-0
  142. pand x0, xmask0f ;Mask high src nibble in bits 4-0
  143. pand xtmpa, xmask0f ;Mask low src nibble in bits 4-0
  144. pshufb xtmph, x0 ;Lookup mul table of high nibble
  145. pshufb xtmpl, xtmpa ;Lookup mul table of low nibble
  146. pxor xtmph, xtmpl ;GF add high and low partials
  147. pxor xd, xtmph
  148. XSTR [dest+pos], xd ;Store result
  149. add pos, 16 ;Loop on 16 bytes at a time
  150. cmp pos, len
  151. jle .loop16
  152. lea tmp, [len + 16]
  153. cmp pos, tmp
  154. je .return_pass
  155. ;; Tail len
  156. mov pos, len ;Overlapped offset length-16
  157. movdqa xd, xtmpd ;Restore xd
  158. jmp .loop16_overlap ;Do one more overlap pass
  159. .return_pass:
  160. mov return, 0
  161. FUNC_RESTORE
  162. ret
  163. .return_fail:
  164. mov return, 1
  165. FUNC_RESTORE
  166. ret
  167. endproc_frame
  168. section .data
  169. align 16
  170. mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
  171. ;;; func core, ver, snum
  172. slversion gf_vect_mad_sse, 00, 01, 0200