AggressiveInstCombineInternal.h 4.9 KB

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  1. //===- AggressiveInstCombineInternal.h --------------------------*- C++ -*-===//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //===----------------------------------------------------------------------===//
  8. //
  9. // This file implements the instruction pattern combiner classes.
  10. // Currently, it handles pattern expressions for:
  11. // * Truncate instruction
  12. //
  13. //===----------------------------------------------------------------------===//
  14. #ifndef LLVM_LIB_TRANSFORMS_AGGRESSIVEINSTCOMBINE_COMBINEINTERNAL_H
  15. #define LLVM_LIB_TRANSFORMS_AGGRESSIVEINSTCOMBINE_COMBINEINTERNAL_H
  16. #include "llvm/ADT/MapVector.h"
  17. #include "llvm/ADT/SmallVector.h"
  18. using namespace llvm;
  19. //===----------------------------------------------------------------------===//
  20. // TruncInstCombine - looks for expression dags dominated by trunc instructions
  21. // and for each eligible dag, it will create a reduced bit-width expression and
  22. // replace the old expression with this new one and remove the old one.
  23. // Eligible expression dag is such that:
  24. // 1. Contains only supported instructions.
  25. // 2. Supported leaves: ZExtInst, SExtInst, TruncInst and Constant value.
  26. // 3. Can be evaluated into type with reduced legal bit-width (or Trunc type).
  27. // 4. All instructions in the dag must not have users outside the dag.
  28. // Only exception is for {ZExt, SExt}Inst with operand type equal to the
  29. // new reduced type chosen in (3).
  30. //
  31. // The motivation for this optimization is that evaluating and expression using
  32. // smaller bit-width is preferable, especially for vectorization where we can
  33. // fit more values in one vectorized instruction. In addition, this optimization
  34. // may decrease the number of cast instructions, but will not increase it.
  35. //===----------------------------------------------------------------------===//
  36. namespace llvm {
  37. class DataLayout;
  38. class DominatorTree;
  39. class Function;
  40. class Instruction;
  41. class TargetLibraryInfo;
  42. class TruncInst;
  43. class Type;
  44. class Value;
  45. class TruncInstCombine {
  46. TargetLibraryInfo &TLI;
  47. const DataLayout &DL;
  48. const DominatorTree &DT;
  49. /// List of all TruncInst instructions to be processed.
  50. SmallVector<TruncInst *, 4> Worklist;
  51. /// Current processed TruncInst instruction.
  52. TruncInst *CurrentTruncInst;
  53. /// Information per each instruction in the expression dag.
  54. struct Info {
  55. /// Number of LSBs that are needed to generate a valid expression.
  56. unsigned ValidBitWidth = 0;
  57. /// Minimum number of LSBs needed to generate the ValidBitWidth.
  58. unsigned MinBitWidth = 0;
  59. /// The reduced value generated to replace the old instruction.
  60. Value *NewValue = nullptr;
  61. };
  62. /// An ordered map representing expression dag post-dominated by current
  63. /// processed TruncInst. It maps each instruction in the dag to its Info
  64. /// structure. The map is ordered such that each instruction appears before
  65. /// all other instructions in the dag that uses it.
  66. MapVector<Instruction *, Info> InstInfoMap;
  67. public:
  68. TruncInstCombine(TargetLibraryInfo &TLI, const DataLayout &DL,
  69. const DominatorTree &DT)
  70. : TLI(TLI), DL(DL), DT(DT), CurrentTruncInst(nullptr) {}
  71. /// Perform TruncInst pattern optimization on given function.
  72. bool run(Function &F);
  73. private:
  74. /// Build expression dag dominated by the /p CurrentTruncInst and append it to
  75. /// the InstInfoMap container.
  76. ///
  77. /// \return true only if succeed to generate an eligible sub expression dag.
  78. bool buildTruncExpressionDag();
  79. /// Calculate the minimal allowed bit-width of the chain ending with the
  80. /// currently visited truncate's operand.
  81. ///
  82. /// \return minimum number of bits to which the chain ending with the
  83. /// truncate's operand can be shrunk to.
  84. unsigned getMinBitWidth();
  85. /// Build an expression dag dominated by the current processed TruncInst and
  86. /// Check if it is eligible to be reduced to a smaller type.
  87. ///
  88. /// \return the scalar version of the new type to be used for the reduced
  89. /// expression dag, or nullptr if the expression dag is not eligible
  90. /// to be reduced.
  91. Type *getBestTruncatedType();
  92. /// Given a \p V value and a \p SclTy scalar type return the generated reduced
  93. /// value of \p V based on the type \p SclTy.
  94. ///
  95. /// \param V value to be reduced.
  96. /// \param SclTy scalar version of new type to reduce to.
  97. /// \return the new reduced value.
  98. Value *getReducedOperand(Value *V, Type *SclTy);
  99. /// Create a new expression dag using the reduced /p SclTy type and replace
  100. /// the old expression dag with it. Also erase all instructions in the old
  101. /// dag, except those that are still needed outside the dag.
  102. ///
  103. /// \param SclTy scalar version of new type to reduce expression dag into.
  104. void ReduceExpressionDag(Type *SclTy);
  105. };
  106. } // end namespace llvm.
  107. #endif