AArch64Combine.td 5.9 KB

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  1. //=- AArch64.td - Define AArch64 Combine Rules ---------------*- tablegen -*-=//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //===----------------------------------------------------------------------===//
  8. //
  9. //
  10. //===----------------------------------------------------------------------===//
  11. include "llvm/Target/GlobalISel/Combine.td"
  12. def fconstant_to_constant : GICombineRule<
  13. (defs root:$root),
  14. (match (wip_match_opcode G_FCONSTANT):$root,
  15. [{ return matchFConstantToConstant(*${root}, MRI); }]),
  16. (apply [{ applyFConstantToConstant(*${root}); }])>;
  17. def AArch64PreLegalizerCombinerHelper: GICombinerHelper<
  18. "AArch64GenPreLegalizerCombinerHelper", [all_combines,
  19. fconstant_to_constant]> {
  20. let DisableRuleOption = "aarch64prelegalizercombiner-disable-rule";
  21. let StateClass = "AArch64PreLegalizerCombinerHelperState";
  22. let AdditionalArguments = [];
  23. }
  24. // Matchdata for combines which replace a G_SHUFFLE_VECTOR with a
  25. // target-specific opcode.
  26. def shuffle_matchdata : GIDefMatchData<"ShuffleVectorPseudo">;
  27. def rev : GICombineRule<
  28. (defs root:$root, shuffle_matchdata:$matchinfo),
  29. (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
  30. [{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
  31. (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
  32. >;
  33. def zip : GICombineRule<
  34. (defs root:$root, shuffle_matchdata:$matchinfo),
  35. (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
  36. [{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
  37. (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
  38. >;
  39. def uzp : GICombineRule<
  40. (defs root:$root, shuffle_matchdata:$matchinfo),
  41. (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
  42. [{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
  43. (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
  44. >;
  45. def dup: GICombineRule <
  46. (defs root:$root, shuffle_matchdata:$matchinfo),
  47. (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
  48. [{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
  49. (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
  50. >;
  51. def trn : GICombineRule<
  52. (defs root:$root, shuffle_matchdata:$matchinfo),
  53. (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
  54. [{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
  55. (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
  56. >;
  57. def ext: GICombineRule <
  58. (defs root:$root, shuffle_matchdata:$matchinfo),
  59. (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
  60. [{ return matchEXT(*${root}, MRI, ${matchinfo}); }]),
  61. (apply [{ applyEXT(*${root}, ${matchinfo}); }])
  62. >;
  63. // Combines which replace a G_SHUFFLE_VECTOR with a target-specific pseudo
  64. // instruction.
  65. def shuffle_vector_pseudos : GICombineGroup<[dup, rev, ext, zip, uzp, trn]>;
  66. def vashr_vlshr_imm_matchdata : GIDefMatchData<"int64_t">;
  67. def vashr_vlshr_imm : GICombineRule<
  68. (defs root:$root, vashr_vlshr_imm_matchdata:$matchinfo),
  69. (match (wip_match_opcode G_ASHR, G_LSHR):$root,
  70. [{ return matchVAshrLshrImm(*${root}, MRI, ${matchinfo}); }]),
  71. (apply [{ applyVAshrLshrImm(*${root}, MRI, ${matchinfo}); }])
  72. >;
  73. def form_duplane_matchdata :
  74. GIDefMatchData<"std::pair<unsigned, int>">;
  75. def form_duplane : GICombineRule <
  76. (defs root:$root, form_duplane_matchdata:$matchinfo),
  77. (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
  78. [{ return matchDupLane(*${root}, MRI, ${matchinfo}); }]),
  79. (apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }])
  80. >;
  81. def adjust_icmp_imm_matchdata :
  82. GIDefMatchData<"std::pair<uint64_t, CmpInst::Predicate>">;
  83. def adjust_icmp_imm : GICombineRule <
  84. (defs root:$root, adjust_icmp_imm_matchdata:$matchinfo),
  85. (match (wip_match_opcode G_ICMP):$root,
  86. [{ return matchAdjustICmpImmAndPred(*${root}, MRI, ${matchinfo}); }]),
  87. (apply [{ applyAdjustICmpImmAndPred(*${root}, ${matchinfo}, B, Observer); }])
  88. >;
  89. def icmp_lowering : GICombineGroup<[adjust_icmp_imm]>;
  90. def extractvecelt_pairwise_add_matchdata : GIDefMatchData<"std::tuple<unsigned, LLT, Register>">;
  91. def extractvecelt_pairwise_add : GICombineRule<
  92. (defs root:$root, extractvecelt_pairwise_add_matchdata:$matchinfo),
  93. (match (wip_match_opcode G_EXTRACT_VECTOR_ELT):$root,
  94. [{ return matchExtractVecEltPairwiseAdd(*${root}, MRI, ${matchinfo}); }]),
  95. (apply [{ applyExtractVecEltPairwiseAdd(*${root}, MRI, B, ${matchinfo}); }])
  96. >;
  97. def mul_const_matchdata : GIDefMatchData<"std::function<void(MachineIRBuilder&, Register)>">;
  98. def mul_const : GICombineRule<
  99. (defs root:$root, mul_const_matchdata:$matchinfo),
  100. (match (wip_match_opcode G_MUL):$root,
  101. [{ return matchAArch64MulConstCombine(*${root}, MRI, ${matchinfo}); }]),
  102. (apply [{ applyAArch64MulConstCombine(*${root}, MRI, B, ${matchinfo}); }])
  103. >;
  104. // Post-legalization combines which should happen at all optimization levels.
  105. // (E.g. ones that facilitate matching for the selector) For example, matching
  106. // pseudos.
  107. def AArch64PostLegalizerLoweringHelper
  108. : GICombinerHelper<"AArch64GenPostLegalizerLoweringHelper",
  109. [shuffle_vector_pseudos, vashr_vlshr_imm,
  110. icmp_lowering, form_duplane]> {
  111. let DisableRuleOption = "aarch64postlegalizerlowering-disable-rule";
  112. }
  113. // Post-legalization combines which are primarily optimizations.
  114. def AArch64PostLegalizerCombinerHelper
  115. : GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
  116. [copy_prop, erase_undef_store, combines_for_extload,
  117. sext_trunc_sextload,
  118. hoist_logic_op_with_same_opcode_hands,
  119. redundant_and, xor_of_and_with_same_reg,
  120. extractvecelt_pairwise_add, redundant_or,
  121. mul_const]> {
  122. let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
  123. }