CodeGenCommonISel.cpp 6.2 KB

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  1. //===-- CodeGenCommonISel.cpp ---------------------------------------------===//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //===----------------------------------------------------------------------===//
  8. //
  9. // This file defines common utilies that are shared between SelectionDAG and
  10. // GlobalISel frameworks.
  11. //
  12. //===----------------------------------------------------------------------===//
  13. #include "llvm/CodeGen/CodeGenCommonISel.h"
  14. #include "llvm/Analysis/BranchProbabilityInfo.h"
  15. #include "llvm/CodeGen/MachineBasicBlock.h"
  16. #include "llvm/CodeGen/MachineFunction.h"
  17. #include "llvm/CodeGen/TargetInstrInfo.h"
  18. #include "llvm/CodeGen/TargetOpcodes.h"
  19. using namespace llvm;
  20. /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
  21. /// is 0.
  22. MachineBasicBlock *
  23. StackProtectorDescriptor::addSuccessorMBB(
  24. const BasicBlock *BB, MachineBasicBlock *ParentMBB, bool IsLikely,
  25. MachineBasicBlock *SuccMBB) {
  26. // If SuccBB has not been created yet, create it.
  27. if (!SuccMBB) {
  28. MachineFunction *MF = ParentMBB->getParent();
  29. MachineFunction::iterator BBI(ParentMBB);
  30. SuccMBB = MF->CreateMachineBasicBlock(BB);
  31. MF->insert(++BBI, SuccMBB);
  32. }
  33. // Add it as a successor of ParentMBB.
  34. ParentMBB->addSuccessor(
  35. SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
  36. return SuccMBB;
  37. }
  38. /// Given that the input MI is before a partial terminator sequence TSeq, return
  39. /// true if M + TSeq also a partial terminator sequence.
  40. ///
  41. /// A Terminator sequence is a sequence of MachineInstrs which at this point in
  42. /// lowering copy vregs into physical registers, which are then passed into
  43. /// terminator instructors so we can satisfy ABI constraints. A partial
  44. /// terminator sequence is an improper subset of a terminator sequence (i.e. it
  45. /// may be the whole terminator sequence).
  46. static bool MIIsInTerminatorSequence(const MachineInstr &MI) {
  47. // If we do not have a copy or an implicit def, we return true if and only if
  48. // MI is a debug value.
  49. if (!MI.isCopy() && !MI.isImplicitDef()) {
  50. // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
  51. // physical registers if there is debug info associated with the terminator
  52. // of our mbb. We want to include said debug info in our terminator
  53. // sequence, so we return true in that case.
  54. if (MI.isDebugInstr())
  55. return true;
  56. // For GlobalISel, we may have extension instructions for arguments within
  57. // copy sequences. Allow these.
  58. switch (MI.getOpcode()) {
  59. case TargetOpcode::G_TRUNC:
  60. case TargetOpcode::G_ZEXT:
  61. case TargetOpcode::G_ANYEXT:
  62. case TargetOpcode::G_SEXT:
  63. case TargetOpcode::G_MERGE_VALUES:
  64. case TargetOpcode::G_UNMERGE_VALUES:
  65. case TargetOpcode::G_CONCAT_VECTORS:
  66. case TargetOpcode::G_BUILD_VECTOR:
  67. case TargetOpcode::G_EXTRACT:
  68. return true;
  69. default:
  70. return false;
  71. }
  72. }
  73. // We have left the terminator sequence if we are not doing one of the
  74. // following:
  75. //
  76. // 1. Copying a vreg into a physical register.
  77. // 2. Copying a vreg into a vreg.
  78. // 3. Defining a register via an implicit def.
  79. // OPI should always be a register definition...
  80. MachineInstr::const_mop_iterator OPI = MI.operands_begin();
  81. if (!OPI->isReg() || !OPI->isDef())
  82. return false;
  83. // Defining any register via an implicit def is always ok.
  84. if (MI.isImplicitDef())
  85. return true;
  86. // Grab the copy source...
  87. MachineInstr::const_mop_iterator OPI2 = OPI;
  88. ++OPI2;
  89. assert(OPI2 != MI.operands_end()
  90. && "Should have a copy implying we should have 2 arguments.");
  91. // Make sure that the copy dest is not a vreg when the copy source is a
  92. // physical register.
  93. if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) &&
  94. Register::isPhysicalRegister(OPI2->getReg())))
  95. return false;
  96. return true;
  97. }
  98. /// Find the split point at which to splice the end of BB into its success stack
  99. /// protector check machine basic block.
  100. ///
  101. /// On many platforms, due to ABI constraints, terminators, even before register
  102. /// allocation, use physical registers. This creates an issue for us since
  103. /// physical registers at this point can not travel across basic
  104. /// blocks. Luckily, selectiondag always moves physical registers into vregs
  105. /// when they enter functions and moves them through a sequence of copies back
  106. /// into the physical registers right before the terminator creating a
  107. /// ``Terminator Sequence''. This function is searching for the beginning of the
  108. /// terminator sequence so that we can ensure that we splice off not just the
  109. /// terminator, but additionally the copies that move the vregs into the
  110. /// physical registers.
  111. MachineBasicBlock::iterator
  112. llvm::findSplitPointForStackProtector(MachineBasicBlock *BB,
  113. const TargetInstrInfo &TII) {
  114. MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
  115. if (SplitPoint == BB->begin())
  116. return SplitPoint;
  117. MachineBasicBlock::iterator Start = BB->begin();
  118. MachineBasicBlock::iterator Previous = SplitPoint;
  119. --Previous;
  120. if (TII.isTailCall(*SplitPoint) &&
  121. Previous->getOpcode() == TII.getCallFrameDestroyOpcode()) {
  122. // Call frames cannot be nested, so if this frame is describing the tail
  123. // call itself, then we must insert before the sequence even starts. For
  124. // example:
  125. // <split point>
  126. // ADJCALLSTACKDOWN ...
  127. // <Moves>
  128. // ADJCALLSTACKUP ...
  129. // TAILJMP somewhere
  130. // On the other hand, it could be an unrelated call in which case this tail
  131. // call has to register moves of its own and should be the split point. For
  132. // example:
  133. // ADJCALLSTACKDOWN
  134. // CALL something_else
  135. // ADJCALLSTACKUP
  136. // <split point>
  137. // TAILJMP somewhere
  138. do {
  139. --Previous;
  140. if (Previous->isCall())
  141. return SplitPoint;
  142. } while(Previous->getOpcode() != TII.getCallFrameSetupOpcode());
  143. return Previous;
  144. }
  145. while (MIIsInTerminatorSequence(*Previous)) {
  146. SplitPoint = Previous;
  147. if (Previous == Start)
  148. break;
  149. --Previous;
  150. }
  151. return SplitPoint;
  152. }