gf_vect_dot_prod_avx512.asm 6.2 KB

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  1. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  2. ; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
  3. ;
  4. ; Redistribution and use in source and binary forms, with or without
  5. ; modification, are permitted provided that the following conditions
  6. ; are met:
  7. ; * Redistributions of source code must retain the above copyright
  8. ; notice, this list of conditions and the following disclaimer.
  9. ; * Redistributions in binary form must reproduce the above copyright
  10. ; notice, this list of conditions and the following disclaimer in
  11. ; the documentation and/or other materials provided with the
  12. ; distribution.
  13. ; * Neither the name of Intel Corporation nor the names of its
  14. ; contributors may be used to endorse or promote products derived
  15. ; from this software without specific prior written permission.
  16. ;
  17. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20. ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21. ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22. ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23. ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24. ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25. ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26. ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29. ;;;
  30. ;;; gf_vect_dot_prod_avx512(len, vec, *g_tbls, **buffs, *dest);
  31. ;;;
  32. %include "reg_sizes.asm"
  33. %ifdef HAVE_AS_KNOWS_AVX512
  34. %ifidn __OUTPUT_FORMAT__, elf64
  35. %define arg0 rdi
  36. %define arg1 rsi
  37. %define arg2 rdx
  38. %define arg3 rcx
  39. %define arg4 r8
  40. %define arg5 r9
  41. %define tmp r11
  42. %define tmp2 r10
  43. %define return rax
  44. %define PS 8
  45. %define LOG_PS 3
  46. %define func(x) x:
  47. %define FUNC_SAVE
  48. %define FUNC_RESTORE
  49. %endif
  50. %ifidn __OUTPUT_FORMAT__, win64
  51. %define arg0 rcx
  52. %define arg1 rdx
  53. %define arg2 r8
  54. %define arg3 r9
  55. %define arg4 r12 ; must be saved, loaded and restored
  56. %define arg5 r15 ; must be saved and restored
  57. %define tmp r11
  58. %define tmp2 r10
  59. %define return rax
  60. %define PS 8
  61. %define LOG_PS 3
  62. %define stack_size 0*16 + 3*8 ; must be an odd multiple of 8
  63. %define arg(x) [rsp + stack_size + PS + PS*x]
  64. %define func(x) proc_frame x
  65. %macro FUNC_SAVE 0
  66. alloc_stack stack_size
  67. save_reg r12, 9*16 + 0*8
  68. save_reg r15, 9*16 + 3*8
  69. end_prolog
  70. mov arg4, arg(4)
  71. %endmacro
  72. %macro FUNC_RESTORE 0
  73. mov r12, [rsp + 9*16 + 0*8]
  74. mov r15, [rsp + 9*16 + 3*8]
  75. add rsp, stack_size
  76. %endmacro
  77. %endif
  78. %define len arg0
  79. %define vec arg1
  80. %define mul_array arg2
  81. %define src arg3
  82. %define dest1 arg4
  83. %define ptr arg5
  84. %define vec_i tmp2
  85. %define pos return
  86. %ifndef EC_ALIGNED_ADDR
  87. ;;; Use Un-aligned load/store
  88. %define XLDR vmovdqu8
  89. %define XSTR vmovdqu8
  90. %else
  91. ;;; Use Non-temporal load/stor
  92. %ifdef NO_NT_LDST
  93. %define XLDR vmovdqa
  94. %define XSTR vmovdqa
  95. %else
  96. %define XLDR vmovntdqa
  97. %define XSTR vmovntdq
  98. %endif
  99. %endif
  100. %define xmask0f zmm5
  101. %define xgft1_lo zmm4
  102. %define xgft1_loy ymm4
  103. %define xgft1_hi zmm3
  104. %define x0 zmm0
  105. %define xgft1_loy ymm4
  106. %define x0y ymm0
  107. %define xtmpa zmm1
  108. %define xp1 zmm2
  109. %define xp1y ymm2
  110. default rel
  111. [bits 64]
  112. section .text
  113. align 16
  114. global gf_vect_dot_prod_avx512:ISAL_SYM_TYPE_FUNCTION
  115. func(gf_vect_dot_prod_avx512)
  116. %ifidn __OUTPUT_FORMAT__, macho64
  117. global _gf_vect_dot_prod_avx512:ISAL_SYM_TYPE_FUNCTION
  118. func(_gf_vect_dot_prod_avx512)
  119. %endif
  120. FUNC_SAVE
  121. xor pos, pos
  122. mov tmp, 0x0f
  123. vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
  124. sal vec, LOG_PS ;vec *= PS. Make vec_i count by PS
  125. sub len, 64
  126. jl .len_lt_64
  127. .loop64:
  128. vpxorq xp1, xp1, xp1
  129. mov tmp, mul_array
  130. xor vec_i, vec_i
  131. .next_vect:
  132. mov ptr, [src+vec_i]
  133. XLDR x0, [ptr+pos] ;Get next source vector
  134. add vec_i, PS
  135. vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
  136. vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
  137. vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
  138. vmovdqu8 xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
  139. add tmp, 32
  140. vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x55
  141. vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x00
  142. vpshufb xgft1_hi, xgft1_hi, x0 ;Lookup mul table of high nibble
  143. vpshufb xgft1_lo, xgft1_lo, xtmpa ;Lookup mul table of low nibble
  144. vpxorq xgft1_hi, xgft1_hi, xgft1_lo ;GF add high and low partials
  145. vpxorq xp1, xp1, xgft1_hi ;xp1 += partial
  146. cmp vec_i, vec
  147. jl .next_vect
  148. XSTR [dest1+pos], xp1
  149. add pos, 64 ;Loop on 64 bytes at a time
  150. cmp pos, len
  151. jle .loop64
  152. lea tmp, [len + 64]
  153. cmp pos, tmp
  154. je .return_pass
  155. ;; Tail len
  156. mov pos, len ;Overlapped offset length-64
  157. jmp .loop64 ;Do one more overlap pass
  158. .len_lt_64: ; 32-byte version
  159. add len, 32
  160. jl .return_fail
  161. .loop32:
  162. vpxorq xp1, xp1, xp1
  163. mov tmp, mul_array
  164. xor vec_i, vec_i
  165. .next_vect2:
  166. mov ptr, [src+vec_i]
  167. XLDR x0y, [ptr+pos] ;Get next source vector 32B
  168. add vec_i, PS
  169. vpsraw xtmpa, x0, 4 ;Shift to put high nibble into bits 4-0
  170. vshufi64x2 x0, x0, xtmpa, 0x44 ;put x0 = xl:xh
  171. vpandq x0, x0, xmask0f ;Mask bits 4-0
  172. vmovdqu8 xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
  173. add tmp, 32
  174. vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x50 ;=AlAh:AlAh
  175. vpshufb xgft1_lo, xgft1_lo, x0 ;Lookup mul table
  176. vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x0e ;=xh:
  177. vpxorq xgft1_hi, xgft1_hi, xgft1_lo ;GF add high and low partials
  178. vpxorq xp1, xp1, xgft1_hi ;xp1 += partial
  179. cmp vec_i, vec
  180. jl .next_vect2
  181. XSTR [dest1+pos], xp1y
  182. add pos, 32 ;Loop on 32 bytes at a time
  183. cmp pos, len
  184. jle .loop32
  185. lea tmp, [len + 32]
  186. cmp pos, tmp
  187. je .return_pass
  188. ;; Tail len
  189. mov pos, len ;Overlapped offset length-32
  190. jmp .loop32 ;Do one more overlap pass
  191. .return_pass:
  192. mov return, 0
  193. FUNC_RESTORE
  194. ret
  195. .return_fail:
  196. mov return, 1
  197. FUNC_RESTORE
  198. ret
  199. endproc_frame
  200. %else
  201. %ifidn __OUTPUT_FORMAT__, win64
  202. global no_gf_vect_dot_prod_avx512
  203. no_gf_vect_dot_prod_avx512:
  204. %endif
  205. %endif ; ifdef HAVE_AS_KNOWS_AVX512