gf_3vect_dot_prod_avx512.asm 7.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275
  1. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  2. ; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
  3. ;
  4. ; Redistribution and use in source and binary forms, with or without
  5. ; modification, are permitted provided that the following conditions
  6. ; are met:
  7. ; * Redistributions of source code must retain the above copyright
  8. ; notice, this list of conditions and the following disclaimer.
  9. ; * Redistributions in binary form must reproduce the above copyright
  10. ; notice, this list of conditions and the following disclaimer in
  11. ; the documentation and/or other materials provided with the
  12. ; distribution.
  13. ; * Neither the name of Intel Corporation nor the names of its
  14. ; contributors may be used to endorse or promote products derived
  15. ; from this software without specific prior written permission.
  16. ;
  17. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18. ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19. ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20. ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21. ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22. ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23. ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24. ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25. ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26. ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29. ;;;
  30. ;;; gf_3vect_dot_prod_avx512(len, vec, *g_tbls, **buffs, **dests);
  31. ;;;
  32. %include "reg_sizes.asm"
  33. %ifdef HAVE_AS_KNOWS_AVX512
  34. %ifidn __OUTPUT_FORMAT__, elf64
  35. %define arg0 rdi
  36. %define arg1 rsi
  37. %define arg2 rdx
  38. %define arg3 rcx
  39. %define arg4 r8
  40. %define arg5 r9
  41. %define tmp r11
  42. %define tmp.w r11d
  43. %define tmp.b r11b
  44. %define tmp2 r10
  45. %define tmp3 r13 ; must be saved and restored
  46. %define tmp4 r12 ; must be saved and restored
  47. %define return rax
  48. %define PS 8
  49. %define LOG_PS 3
  50. %define func(x) x:
  51. %macro FUNC_SAVE 0
  52. push r12
  53. push r13
  54. %endmacro
  55. %macro FUNC_RESTORE 0
  56. pop r13
  57. pop r12
  58. %endmacro
  59. %endif
  60. %ifidn __OUTPUT_FORMAT__, win64
  61. %define arg0 rcx
  62. %define arg1 rdx
  63. %define arg2 r8
  64. %define arg3 r9
  65. %define arg4 r12 ; must be saved, loaded and restored
  66. %define arg5 r15 ; must be saved and restored
  67. %define tmp r11
  68. %define tmp.w r11d
  69. %define tmp.b r11b
  70. %define tmp2 r10
  71. %define tmp3 r13 ; must be saved and restored
  72. %define tmp4 r14 ; must be saved and restored
  73. %define return rax
  74. %define PS 8
  75. %define LOG_PS 3
  76. %define stack_size 9*16 + 5*8 ; must be an odd multiple of 8
  77. %define arg(x) [rsp + stack_size + PS + PS*x]
  78. %define func(x) proc_frame x
  79. %macro FUNC_SAVE 0
  80. alloc_stack stack_size
  81. vmovdqa [rsp + 0*16], xmm6
  82. vmovdqa [rsp + 1*16], xmm7
  83. vmovdqa [rsp + 2*16], xmm8
  84. vmovdqa [rsp + 3*16], xmm9
  85. vmovdqa [rsp + 4*16], xmm10
  86. vmovdqa [rsp + 5*16], xmm11
  87. vmovdqa [rsp + 6*16], xmm12
  88. vmovdqa [rsp + 7*16], xmm13
  89. vmovdqa [rsp + 8*16], xmm14
  90. save_reg r12, 9*16 + 0*8
  91. save_reg r13, 9*16 + 1*8
  92. save_reg r14, 9*16 + 2*8
  93. save_reg r15, 9*16 + 3*8
  94. end_prolog
  95. mov arg4, arg(4)
  96. %endmacro
  97. %macro FUNC_RESTORE 0
  98. vmovdqa xmm6, [rsp + 0*16]
  99. vmovdqa xmm7, [rsp + 1*16]
  100. vmovdqa xmm8, [rsp + 2*16]
  101. vmovdqa xmm9, [rsp + 3*16]
  102. vmovdqa xmm10, [rsp + 4*16]
  103. vmovdqa xmm11, [rsp + 5*16]
  104. vmovdqa xmm12, [rsp + 6*16]
  105. vmovdqa xmm13, [rsp + 7*16]
  106. vmovdqa xmm14, [rsp + 8*16]
  107. mov r12, [rsp + 9*16 + 0*8]
  108. mov r13, [rsp + 9*16 + 1*8]
  109. mov r14, [rsp + 9*16 + 2*8]
  110. mov r15, [rsp + 9*16 + 3*8]
  111. add rsp, stack_size
  112. %endmacro
  113. %endif
  114. %define len arg0
  115. %define vec arg1
  116. %define mul_array arg2
  117. %define src arg3
  118. %define dest1 arg4
  119. %define ptr arg5
  120. %define vec_i tmp2
  121. %define dest2 tmp3
  122. %define dest3 tmp4
  123. %define pos return
  124. %ifndef EC_ALIGNED_ADDR
  125. ;;; Use Un-aligned load/store
  126. %define XLDR vmovdqu8
  127. %define XSTR vmovdqu8
  128. %else
  129. ;;; Use Non-temporal load/stor
  130. %ifdef NO_NT_LDST
  131. %define XLDR vmovdqa
  132. %define XSTR vmovdqa
  133. %else
  134. %define XLDR vmovntdqa
  135. %define XSTR vmovntdq
  136. %endif
  137. %endif
  138. %define xmask0f zmm11
  139. %define xgft1_lo zmm10
  140. %define xgft1_loy ymm10
  141. %define xgft1_hi zmm9
  142. %define xgft2_lo zmm8
  143. %define xgft2_loy ymm8
  144. %define xgft2_hi zmm7
  145. %define xgft3_lo zmm6
  146. %define xgft3_loy ymm6
  147. %define xgft3_hi zmm5
  148. %define x0 zmm0
  149. %define xtmpa zmm1
  150. %define xp1 zmm2
  151. %define xp2 zmm3
  152. %define xp3 zmm4
  153. default rel
  154. [bits 64]
  155. section .text
  156. align 16
  157. global gf_3vect_dot_prod_avx512:ISAL_SYM_TYPE_FUNCTION
  158. func(gf_3vect_dot_prod_avx512)
  159. %ifidn __OUTPUT_FORMAT__, macho64
  160. global _gf_3vect_dot_prod_avx512:ISAL_SYM_TYPE_FUNCTION
  161. func(_gf_3vect_dot_prod_avx512)
  162. %endif
  163. FUNC_SAVE
  164. sub len, 64
  165. jl .return_fail
  166. xor pos, pos
  167. mov tmp, 0x0f
  168. vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
  169. sal vec, LOG_PS ;vec *= PS. Make vec_i count by PS
  170. mov dest2, [dest1+PS]
  171. mov dest3, [dest1+2*PS]
  172. mov dest1, [dest1]
  173. .loop64:
  174. vpxorq xp1, xp1, xp1
  175. vpxorq xp2, xp2, xp2
  176. vpxorq xp3, xp3, xp3
  177. mov tmp, mul_array
  178. xor vec_i, vec_i
  179. .next_vect:
  180. mov ptr, [src+vec_i]
  181. XLDR x0, [ptr+pos] ;Get next source vector
  182. add vec_i, PS
  183. vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
  184. vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
  185. vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
  186. vmovdqu8 xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
  187. vmovdqu8 xgft2_loy, [tmp+vec*(32/PS)] ;Load array Bx{00}..{0f}, Bx{00}..{f0}
  188. vmovdqu8 xgft3_loy, [tmp+vec*(64/PS)] ;Load array Cx{00}..{0f}, Cx{00}..{f0}
  189. add tmp, 32
  190. vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x55
  191. vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x00
  192. vshufi64x2 xgft2_hi, xgft2_lo, xgft2_lo, 0x55
  193. vshufi64x2 xgft2_lo, xgft2_lo, xgft2_lo, 0x00
  194. vpshufb xgft1_hi, xgft1_hi, x0 ;Lookup mul table of high nibble
  195. vpshufb xgft1_lo, xgft1_lo, xtmpa ;Lookup mul table of low nibble
  196. vpxorq xgft1_hi, xgft1_hi, xgft1_lo ;GF add high and low partials
  197. vpxorq xp1, xp1, xgft1_hi ;xp1 += partial
  198. vpshufb xgft2_hi, xgft2_hi, x0 ;Lookup mul table of high nibble
  199. vpshufb xgft2_lo, xgft2_lo, xtmpa ;Lookup mul table of low nibble
  200. vpxorq xgft2_hi, xgft2_hi, xgft2_lo ;GF add high and low partials
  201. vpxorq xp2, xp2, xgft2_hi ;xp2 += partial
  202. vshufi64x2 xgft3_hi, xgft3_lo, xgft3_lo, 0x55
  203. vshufi64x2 xgft3_lo, xgft3_lo, xgft3_lo, 0x00
  204. vpshufb xgft3_hi, xgft3_hi, x0 ;Lookup mul table of high nibble
  205. vpshufb xgft3_lo, xgft3_lo, xtmpa ;Lookup mul table of low nibble
  206. vpxorq xgft3_hi, xgft3_hi, xgft3_lo ;GF add high and low partials
  207. vpxorq xp3, xp3, xgft3_hi ;xp3 += partial
  208. cmp vec_i, vec
  209. jl .next_vect
  210. XSTR [dest1+pos], xp1
  211. XSTR [dest2+pos], xp2
  212. XSTR [dest3+pos], xp3
  213. add pos, 64 ;Loop on 64 bytes at a time
  214. cmp pos, len
  215. jle .loop64
  216. lea tmp, [len + 64]
  217. cmp pos, tmp
  218. je .return_pass
  219. ;; Tail len
  220. mov pos, len ;Overlapped offset length-64
  221. jmp .loop64 ;Do one more overlap pass
  222. .return_pass:
  223. mov return, 0
  224. FUNC_RESTORE
  225. ret
  226. .return_fail:
  227. mov return, 1
  228. FUNC_RESTORE
  229. ret
  230. endproc_frame
  231. %else
  232. %ifidn __OUTPUT_FORMAT__, win64
  233. global no_gf_3vect_dot_prod_avx512
  234. no_gf_3vect_dot_prod_avx512:
  235. %endif
  236. %endif ; ifdef HAVE_AS_KNOWS_AVX512