PPCSchedule440.td 35 KB

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  1. //===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
  2. //
  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  4. // See https://llvm.org/LICENSE.txt for license information.
  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  6. //
  7. //===----------------------------------------------------------------------===//
  8. // Primary reference:
  9. // PowerPC 440x6 Embedded Processor Core User's Manual.
  10. // IBM (as updated in) 2010.
  11. // The basic PPC 440 does not include a floating-point unit; the pipeline
  12. // timings here are constructed to match the FP2 unit shipped with the
  13. // PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
  14. // References:
  15. // S. Chatterjee, et al. Design and exploitation of a high-performance
  16. // SIMD floating-point unit for Blue Gene/L.
  17. // IBM J. Res. & Dev. 49 (2/3) March/May 2005.
  18. // also:
  19. // Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
  20. // Blue Gene/P Application Development.
  21. // IBM (as updated in) 2009.
  22. //===----------------------------------------------------------------------===//
  23. // Functional units on the PowerPC 440/450 chip sets
  24. //
  25. def P440_DISS1 : FuncUnit; // Issue unit 1
  26. def P440_DISS2 : FuncUnit; // Issue unit 2
  27. def P440_LRACC : FuncUnit; // Register access and dispatch for
  28. // the simple integer (J-pipe) and
  29. // load/store (L-pipe) pipelines
  30. def P440_IRACC : FuncUnit; // Register access and dispatch for
  31. // the complex integer (I-pipe) pipeline
  32. def P440_FRACC : FuncUnit; // Register access and dispatch for
  33. // the floating-point execution (F-pipe) pipeline
  34. def P440_IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
  35. def P440_IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
  36. def P440_IWB : FuncUnit; // Write-back unit for the I pipeline
  37. def P440_JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
  38. def P440_JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
  39. def P440_JWB : FuncUnit; // Write-back unit for the J pipeline
  40. def P440_AGEN : FuncUnit; // Address generation for the L pipeline
  41. def P440_CRD : FuncUnit; // D-cache access for the L pipeline
  42. def P440_LWB : FuncUnit; // Write-back unit for the L pipeline
  43. def P440_FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline
  44. def P440_FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline
  45. def P440_FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline
  46. def P440_FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline
  47. def P440_FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline
  48. def P440_FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline
  49. def P440_FWB : FuncUnit; // Write-back unit for the F pipeline
  50. def P440_LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
  51. // to make sure that no lwarx/stwcx.
  52. // instructions are issued while another
  53. // lwarx/stwcx. is in the L pipe.
  54. def P440_GPR_Bypass : Bypass; // The bypass for general-purpose regs.
  55. def P440_FPR_Bypass : Bypass; // The bypass for floating-point regs.
  56. // Notes:
  57. // Instructions are held in the FRACC, LRACC and IRACC pipeline
  58. // stages until their source operands become ready. Exceptions:
  59. // - Store instructions will hold in the AGEN stage
  60. // - The integer multiply-accumulate instruction will hold in
  61. // the IEXE1 stage
  62. //
  63. // For most I-pipe operations, the result is available at the end of
  64. // the IEXE1 stage. Operations such as multiply and divide must
  65. // continue to execute in IEXE2 and IWB. Divide resides in IWB for
  66. // 33 cycles (multiply also calculates its result in IWB). For all
  67. // J-pipe instructions, the result is available
  68. // at the end of the JEXE1 stage. Loads have a 3-cycle latency
  69. // (data is not available until after the LWB stage).
  70. //
  71. // The L1 cache hit latency is four cycles for floating point loads
  72. // and three cycles for integer loads.
  73. //
  74. // The stwcx. instruction requires both the LRACC and the IRACC
  75. // dispatch stages. It must be issued from DISS0.
  76. //
  77. // All lwarx/stwcx. instructions hold in LRACC if another
  78. // uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
  79. //
  80. // msync (a.k.a. sync) and mbar will hold in LWB until all load/store
  81. // resources are empty. AGEN and CRD are held empty until the msync/mbar
  82. // commits.
  83. //
  84. // Most floating-point instructions, computational and move,
  85. // have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
  86. // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
  87. // loads take 4 cycles (for L1 hit).
  88. //
  89. // This file defines the itinerary class data for the PPC 440 processor.
  90. //
  91. //===----------------------------------------------------------------------===//
  92. def PPC440Itineraries : ProcessorItineraries<
  93. [P440_DISS1, P440_DISS2, P440_FRACC, P440_IRACC, P440_IEXE1, P440_IEXE2,
  94. P440_IWB, P440_LRACC, P440_JEXE1, P440_JEXE2, P440_JWB, P440_AGEN, P440_CRD,
  95. P440_LWB, P440_FEXE1, P440_FEXE2, P440_FEXE3, P440_FEXE4, P440_FEXE5,
  96. P440_FEXE6, P440_FWB, P440_LWARX_Hold],
  97. [P440_GPR_Bypass, P440_FPR_Bypass], [
  98. InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  99. InstrStage<1, [P440_IRACC, P440_LRACC]>,
  100. InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
  101. InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
  102. InstrStage<1, [P440_IWB, P440_JWB]>],
  103. [2, 0, 0],
  104. [P440_GPR_Bypass,
  105. P440_GPR_Bypass, P440_GPR_Bypass]>,
  106. InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  107. InstrStage<1, [P440_IRACC, P440_LRACC]>,
  108. InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
  109. InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
  110. InstrStage<1, [P440_IWB, P440_JWB]>],
  111. [2, 0, 0],
  112. [P440_GPR_Bypass,
  113. P440_GPR_Bypass, P440_GPR_Bypass]>,
  114. InstrItinData<IIC_IntISEL, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  115. InstrStage<1, [P440_IRACC, P440_LRACC]>,
  116. InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
  117. InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
  118. InstrStage<1, [P440_IWB, P440_JWB]>],
  119. [2, 0, 0, 0],
  120. [P440_GPR_Bypass,
  121. P440_GPR_Bypass, P440_GPR_Bypass, NoBypass]>,
  122. InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  123. InstrStage<1, [P440_IRACC, P440_LRACC]>,
  124. InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
  125. InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
  126. InstrStage<1, [P440_IWB, P440_JWB]>],
  127. [2, 0, 0],
  128. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  129. InstrItinData<IIC_IntDivW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  130. InstrStage<1, [P440_IRACC]>,
  131. InstrStage<1, [P440_IEXE1]>,
  132. InstrStage<1, [P440_IEXE2]>,
  133. InstrStage<33, [P440_IWB]>],
  134. [36, 0, 0],
  135. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  136. InstrItinData<IIC_IntMFFS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  137. InstrStage<1, [P440_IRACC]>,
  138. InstrStage<1, [P440_IEXE1]>,
  139. InstrStage<1, [P440_IEXE2]>,
  140. InstrStage<1, [P440_IWB]>],
  141. [3, 0, 0],
  142. [P440_GPR_Bypass,
  143. P440_GPR_Bypass, P440_GPR_Bypass]>,
  144. InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  145. InstrStage<1, [P440_IRACC]>,
  146. InstrStage<1, [P440_IEXE1]>,
  147. InstrStage<1, [P440_IEXE2]>,
  148. InstrStage<1, [P440_IWB]>],
  149. [3, 0, 0],
  150. [P440_GPR_Bypass,
  151. P440_GPR_Bypass, P440_GPR_Bypass]>,
  152. InstrItinData<IIC_IntMulHW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  153. InstrStage<1, [P440_IRACC]>,
  154. InstrStage<1, [P440_IEXE1]>,
  155. InstrStage<1, [P440_IEXE2]>,
  156. InstrStage<1, [P440_IWB]>],
  157. [4, 0, 0],
  158. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  159. InstrItinData<IIC_IntMulHWU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  160. InstrStage<1, [P440_IRACC]>,
  161. InstrStage<1, [P440_IEXE1]>,
  162. InstrStage<1, [P440_IEXE2]>,
  163. InstrStage<1, [P440_IWB]>],
  164. [4, 0, 0],
  165. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  166. InstrItinData<IIC_IntMulLI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  167. InstrStage<1, [P440_IRACC]>,
  168. InstrStage<1, [P440_IEXE1]>,
  169. InstrStage<1, [P440_IEXE2]>,
  170. InstrStage<1, [P440_IWB]>],
  171. [4, 0, 0],
  172. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  173. InstrItinData<IIC_IntRotate, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  174. InstrStage<1, [P440_IRACC, P440_LRACC]>,
  175. InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
  176. InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
  177. InstrStage<1, [P440_IWB, P440_JWB]>],
  178. [2, 0, 0],
  179. [P440_GPR_Bypass,
  180. P440_GPR_Bypass, P440_GPR_Bypass]>,
  181. InstrItinData<IIC_IntShift, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  182. InstrStage<1, [P440_IRACC, P440_LRACC]>,
  183. InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
  184. InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
  185. InstrStage<1, [P440_IWB, P440_JWB]>],
  186. [2, 0, 0],
  187. [P440_GPR_Bypass,
  188. P440_GPR_Bypass, P440_GPR_Bypass]>,
  189. InstrItinData<IIC_IntTrapW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  190. InstrStage<1, [P440_IRACC]>,
  191. InstrStage<1, [P440_IEXE1]>,
  192. InstrStage<1, [P440_IEXE2]>,
  193. InstrStage<1, [P440_IWB]>],
  194. [2, 0],
  195. [P440_GPR_Bypass, P440_GPR_Bypass]>,
  196. InstrItinData<IIC_BrB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  197. InstrStage<1, [P440_IRACC]>,
  198. InstrStage<1, [P440_IEXE1]>,
  199. InstrStage<1, [P440_IEXE2]>,
  200. InstrStage<1, [P440_IWB]>],
  201. [4, 0],
  202. [NoBypass, P440_GPR_Bypass]>,
  203. InstrItinData<IIC_BrCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  204. InstrStage<1, [P440_IRACC]>,
  205. InstrStage<1, [P440_IEXE1]>,
  206. InstrStage<1, [P440_IEXE2]>,
  207. InstrStage<1, [P440_IWB]>],
  208. [4, 0, 0],
  209. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  210. InstrItinData<IIC_BrMCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  211. InstrStage<1, [P440_IRACC]>,
  212. InstrStage<1, [P440_IEXE1]>,
  213. InstrStage<1, [P440_IEXE2]>,
  214. InstrStage<1, [P440_IWB]>],
  215. [4, 0, 0],
  216. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  217. InstrItinData<IIC_BrMCRX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  218. InstrStage<1, [P440_IRACC]>,
  219. InstrStage<1, [P440_IEXE1]>,
  220. InstrStage<1, [P440_IEXE2]>,
  221. InstrStage<1, [P440_IWB]>],
  222. [4, 0, 0],
  223. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  224. InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  225. InstrStage<1, [P440_LRACC]>,
  226. InstrStage<1, [P440_AGEN]>,
  227. InstrStage<1, [P440_CRD]>,
  228. InstrStage<1, [P440_LWB]>],
  229. [1, 1],
  230. [NoBypass, P440_GPR_Bypass]>,
  231. InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  232. InstrStage<1, [P440_LRACC]>,
  233. InstrStage<1, [P440_AGEN]>,
  234. InstrStage<1, [P440_CRD]>,
  235. InstrStage<1, [P440_LWB]>],
  236. [1, 1],
  237. [NoBypass, P440_GPR_Bypass]>,
  238. InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  239. InstrStage<1, [P440_LRACC]>,
  240. InstrStage<1, [P440_AGEN]>,
  241. InstrStage<1, [P440_CRD]>,
  242. InstrStage<1, [P440_LWB]>],
  243. [1, 1],
  244. [NoBypass, P440_GPR_Bypass]>,
  245. InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  246. InstrStage<1, [P440_LRACC]>,
  247. InstrStage<1, [P440_AGEN]>,
  248. InstrStage<1, [P440_CRD]>,
  249. InstrStage<2, [P440_LWB]>],
  250. [5, 1, 1],
  251. [P440_GPR_Bypass, P440_GPR_Bypass]>,
  252. InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
  253. InstrStage<1, [P440_LRACC]>,
  254. InstrStage<1, [P440_AGEN]>,
  255. InstrStage<1, [P440_CRD]>,
  256. InstrStage<2, [P440_LWB]>],
  257. [5, 2, 1, 1],
  258. [P440_GPR_Bypass, P440_GPR_Bypass]>,
  259. InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
  260. InstrStage<1, [P440_LRACC]>,
  261. InstrStage<1, [P440_AGEN]>,
  262. InstrStage<1, [P440_CRD]>,
  263. InstrStage<2, [P440_LWB]>],
  264. [5, 2, 1, 1],
  265. [P440_GPR_Bypass, P440_GPR_Bypass]>,
  266. InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  267. InstrStage<1, [P440_LRACC]>,
  268. InstrStage<1, [P440_AGEN]>,
  269. InstrStage<1, [P440_CRD]>,
  270. InstrStage<2, [P440_LWB]>],
  271. [1, 1, 1],
  272. [NoBypass, P440_GPR_Bypass]>,
  273. InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  274. InstrStage<1, [P440_LRACC]>,
  275. InstrStage<1, [P440_AGEN]>,
  276. InstrStage<1, [P440_CRD]>,
  277. InstrStage<1, [P440_LWB]>],
  278. [4, 1, 1],
  279. [NoBypass, P440_GPR_Bypass]>,
  280. InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  281. InstrStage<1, [P440_LRACC]>,
  282. InstrStage<1, [P440_AGEN]>,
  283. InstrStage<1, [P440_CRD]>,
  284. InstrStage<1, [P440_LWB]>],
  285. [1, 1, 1],
  286. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  287. InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  288. InstrStage<1, [P440_LRACC]>,
  289. InstrStage<1, [P440_AGEN]>,
  290. InstrStage<1, [P440_CRD]>,
  291. InstrStage<1, [P440_LWB]>],
  292. [2, 1, 1, 1],
  293. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  294. InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  295. InstrStage<1, [P440_LRACC]>,
  296. InstrStage<1, [P440_AGEN]>,
  297. InstrStage<1, [P440_CRD]>,
  298. InstrStage<2, [P440_LWB]>],
  299. [5, 1, 1],
  300. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  301. InstrItinData<IIC_LdStLFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  302. InstrStage<1, [P440_LRACC]>,
  303. InstrStage<1, [P440_AGEN]>,
  304. InstrStage<1, [P440_CRD]>,
  305. InstrStage<1, [P440_LWB]>],
  306. [5, 2, 1, 1],
  307. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  308. InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  309. InstrStage<1, [P440_LRACC]>,
  310. InstrStage<1, [P440_AGEN]>,
  311. InstrStage<1, [P440_CRD]>,
  312. InstrStage<1, [P440_LWB]>],
  313. [5, 2, 1, 1],
  314. [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
  315. InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  316. InstrStage<1, [P440_LRACC]>,
  317. InstrStage<1, [P440_AGEN]>,
  318. InstrStage<1, [P440_CRD]>,
  319. InstrStage<1, [P440_LWB]>],
  320. [4, 1, 1],
  321. [NoBypass, P440_GPR_Bypass]>,
  322. InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  323. InstrStage<1, [P440_LRACC]>,
  324. InstrStage<1, [P440_AGEN]>,
  325. InstrStage<1, [P440_CRD]>,
  326. InstrStage<1, [P440_LWB]>],
  327. [4, 1, 1],
  328. [NoBypass, P440_GPR_Bypass]>,
  329. InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  330. InstrStage<1, [P440_LRACC]>,
  331. InstrStage<1, [P440_AGEN]>,
  332. InstrStage<1, [P440_CRD]>,
  333. InstrStage<1, [P440_LWB]>],
  334. [4, 1, 1],
  335. [NoBypass, P440_GPR_Bypass]>,
  336. InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  337. InstrStage<1, [P440_LRACC]>,
  338. InstrStage<1, [P440_AGEN]>,
  339. InstrStage<1, [P440_CRD]>,
  340. InstrStage<1, [P440_LWB]>],
  341. [4, 1, 1],
  342. [NoBypass, P440_GPR_Bypass]>,
  343. InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_DISS1]>,
  344. InstrStage<1, [P440_IRACC], 0>,
  345. InstrStage<4, [P440_LWARX_Hold], 0>,
  346. InstrStage<1, [P440_LRACC]>,
  347. InstrStage<1, [P440_AGEN]>,
  348. InstrStage<1, [P440_CRD]>,
  349. InstrStage<1, [P440_LWB]>],
  350. [4, 1, 1],
  351. [NoBypass, P440_GPR_Bypass]>,
  352. InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  353. InstrStage<1, [P440_LRACC]>,
  354. InstrStage<1, [P440_AGEN]>,
  355. InstrStage<1, [P440_CRD]>,
  356. InstrStage<2, [P440_LWB]>],
  357. [4, 1, 1],
  358. [NoBypass, P440_GPR_Bypass]>,
  359. InstrItinData<IIC_LdStSTU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  360. InstrStage<1, [P440_LRACC]>,
  361. InstrStage<1, [P440_AGEN]>,
  362. InstrStage<1, [P440_CRD]>,
  363. InstrStage<2, [P440_LWB]>],
  364. [2, 1, 1, 1],
  365. [NoBypass, P440_GPR_Bypass]>,
  366. InstrItinData<IIC_LdStSTUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  367. InstrStage<1, [P440_LRACC]>,
  368. InstrStage<1, [P440_AGEN]>,
  369. InstrStage<1, [P440_CRD]>,
  370. InstrStage<2, [P440_LWB]>],
  371. [2, 1, 1, 1],
  372. [NoBypass, P440_GPR_Bypass]>,
  373. InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>,
  374. InstrStage<1, [P440_IRACC], 0>,
  375. InstrStage<4, [P440_LWARX_Hold], 0>,
  376. InstrStage<1, [P440_LRACC]>,
  377. InstrStage<1, [P440_AGEN]>,
  378. InstrStage<1, [P440_CRD]>,
  379. InstrStage<1, [P440_LWB]>],
  380. [4, 1, 1],
  381. [NoBypass, P440_GPR_Bypass]>,
  382. InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_DISS1]>,
  383. InstrStage<1, [P440_IRACC], 0>,
  384. InstrStage<4, [P440_LWARX_Hold], 0>,
  385. InstrStage<1, [P440_LRACC]>,
  386. InstrStage<1, [P440_AGEN]>,
  387. InstrStage<1, [P440_CRD]>,
  388. InstrStage<1, [P440_LWB]>],
  389. [4, 1, 1],
  390. [NoBypass, P440_GPR_Bypass]>,
  391. InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  392. InstrStage<1, [P440_LRACC]>,
  393. InstrStage<3, [P440_AGEN], 1>,
  394. InstrStage<2, [P440_CRD], 1>,
  395. InstrStage<1, [P440_LWB]>]>,
  396. InstrItinData<IIC_SprISYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  397. InstrStage<1, [P440_FRACC], 0>,
  398. InstrStage<1, [P440_LRACC], 0>,
  399. InstrStage<1, [P440_IRACC]>,
  400. InstrStage<1, [P440_FEXE1], 0>,
  401. InstrStage<1, [P440_AGEN], 0>,
  402. InstrStage<1, [P440_JEXE1], 0>,
  403. InstrStage<1, [P440_IEXE1]>,
  404. InstrStage<1, [P440_FEXE2], 0>,
  405. InstrStage<1, [P440_CRD], 0>,
  406. InstrStage<1, [P440_JEXE2], 0>,
  407. InstrStage<1, [P440_IEXE2]>,
  408. InstrStage<6, [P440_FEXE3], 0>,
  409. InstrStage<6, [P440_LWB], 0>,
  410. InstrStage<6, [P440_JWB], 0>,
  411. InstrStage<6, [P440_IWB]>]>,
  412. InstrItinData<IIC_SprMFSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  413. InstrStage<1, [P440_IRACC]>,
  414. InstrStage<1, [P440_IEXE1]>,
  415. InstrStage<1, [P440_IEXE2]>,
  416. InstrStage<1, [P440_IWB]>],
  417. [2, 0],
  418. [P440_GPR_Bypass, P440_GPR_Bypass]>,
  419. InstrItinData<IIC_SprMTMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  420. InstrStage<1, [P440_IRACC]>,
  421. InstrStage<1, [P440_IEXE1]>,
  422. InstrStage<1, [P440_IEXE2]>,
  423. InstrStage<1, [P440_IWB]>],
  424. [2, 0],
  425. [P440_GPR_Bypass, P440_GPR_Bypass]>,
  426. InstrItinData<IIC_SprMTSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  427. InstrStage<1, [P440_IRACC]>,
  428. InstrStage<1, [P440_IEXE1]>,
  429. InstrStage<1, [P440_IEXE2]>,
  430. InstrStage<3, [P440_IWB]>],
  431. [5, 0],
  432. [NoBypass, P440_GPR_Bypass]>,
  433. InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  434. InstrStage<1, [P440_IRACC]>,
  435. InstrStage<1, [P440_IEXE1]>,
  436. InstrStage<1, [P440_IEXE2]>,
  437. InstrStage<1, [P440_IWB]>]>,
  438. InstrItinData<IIC_SprMFCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  439. InstrStage<1, [P440_IRACC]>,
  440. InstrStage<1, [P440_IEXE1]>,
  441. InstrStage<1, [P440_IEXE2]>,
  442. InstrStage<1, [P440_IWB]>],
  443. [4, 0],
  444. [NoBypass, P440_GPR_Bypass]>,
  445. InstrItinData<IIC_SprMFMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  446. InstrStage<1, [P440_IRACC]>,
  447. InstrStage<1, [P440_IEXE1]>,
  448. InstrStage<1, [P440_IEXE2]>,
  449. InstrStage<1, [P440_IWB]>],
  450. [3, 0],
  451. [P440_GPR_Bypass, P440_GPR_Bypass]>,
  452. InstrItinData<IIC_SprMFSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  453. InstrStage<1, [P440_IRACC]>,
  454. InstrStage<1, [P440_IEXE1]>,
  455. InstrStage<1, [P440_IEXE2]>,
  456. InstrStage<3, [P440_IWB]>],
  457. [6, 0],
  458. [NoBypass, P440_GPR_Bypass]>,
  459. InstrItinData<IIC_SprMFTB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  460. InstrStage<1, [P440_IRACC]>,
  461. InstrStage<1, [P440_IEXE1]>,
  462. InstrStage<1, [P440_IEXE2]>,
  463. InstrStage<3, [P440_IWB]>],
  464. [6, 0],
  465. [NoBypass, P440_GPR_Bypass]>,
  466. InstrItinData<IIC_SprMTSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  467. InstrStage<1, [P440_IRACC]>,
  468. InstrStage<1, [P440_IEXE1]>,
  469. InstrStage<1, [P440_IEXE2]>,
  470. InstrStage<3, [P440_IWB]>],
  471. [6, 0],
  472. [NoBypass, P440_GPR_Bypass]>,
  473. InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  474. InstrStage<1, [P440_IRACC]>,
  475. InstrStage<1, [P440_IEXE1]>,
  476. InstrStage<1, [P440_IEXE2]>,
  477. InstrStage<3, [P440_IWB]>],
  478. [6, 0],
  479. [NoBypass, P440_GPR_Bypass]>,
  480. InstrItinData<IIC_SprRFI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  481. InstrStage<1, [P440_IRACC]>,
  482. InstrStage<1, [P440_IEXE1]>,
  483. InstrStage<1, [P440_IEXE2]>,
  484. InstrStage<1, [P440_IWB]>],
  485. [4, 0],
  486. [NoBypass, P440_GPR_Bypass]>,
  487. InstrItinData<IIC_SprSC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  488. InstrStage<1, [P440_IRACC]>,
  489. InstrStage<1, [P440_IEXE1]>,
  490. InstrStage<1, [P440_IEXE2]>,
  491. InstrStage<1, [P440_IWB]>],
  492. [4, 0],
  493. [NoBypass, P440_GPR_Bypass]>,
  494. InstrItinData<IIC_FPGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  495. InstrStage<1, [P440_FRACC]>,
  496. InstrStage<1, [P440_FEXE1]>,
  497. InstrStage<1, [P440_FEXE2]>,
  498. InstrStage<1, [P440_FEXE3]>,
  499. InstrStage<1, [P440_FEXE4]>,
  500. InstrStage<1, [P440_FEXE5]>,
  501. InstrStage<1, [P440_FEXE6]>,
  502. InstrStage<1, [P440_FWB]>],
  503. [6, 0, 0],
  504. [P440_FPR_Bypass,
  505. P440_FPR_Bypass, P440_FPR_Bypass]>,
  506. InstrItinData<IIC_FPAddSub, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  507. InstrStage<1, [P440_FRACC]>,
  508. InstrStage<1, [P440_FEXE1]>,
  509. InstrStage<1, [P440_FEXE2]>,
  510. InstrStage<1, [P440_FEXE3]>,
  511. InstrStage<1, [P440_FEXE4]>,
  512. InstrStage<1, [P440_FEXE5]>,
  513. InstrStage<1, [P440_FEXE6]>,
  514. InstrStage<1, [P440_FWB]>],
  515. [6, 0, 0],
  516. [P440_FPR_Bypass,
  517. P440_FPR_Bypass, P440_FPR_Bypass]>,
  518. InstrItinData<IIC_FPCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  519. InstrStage<1, [P440_FRACC]>,
  520. InstrStage<1, [P440_FEXE1]>,
  521. InstrStage<1, [P440_FEXE2]>,
  522. InstrStage<1, [P440_FEXE3]>,
  523. InstrStage<1, [P440_FEXE4]>,
  524. InstrStage<1, [P440_FEXE5]>,
  525. InstrStage<1, [P440_FEXE6]>,
  526. InstrStage<1, [P440_FWB]>],
  527. [6, 0, 0],
  528. [P440_FPR_Bypass, P440_FPR_Bypass,
  529. P440_FPR_Bypass]>,
  530. InstrItinData<IIC_FPDivD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  531. InstrStage<1, [P440_FRACC]>,
  532. InstrStage<1, [P440_FEXE1]>,
  533. InstrStage<1, [P440_FEXE2]>,
  534. InstrStage<1, [P440_FEXE3]>,
  535. InstrStage<1, [P440_FEXE4]>,
  536. InstrStage<1, [P440_FEXE5]>,
  537. InstrStage<1, [P440_FEXE6]>,
  538. InstrStage<25, [P440_FWB]>],
  539. [31, 0, 0],
  540. [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
  541. InstrItinData<IIC_FPDivS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  542. InstrStage<1, [P440_FRACC]>,
  543. InstrStage<1, [P440_FEXE1]>,
  544. InstrStage<1, [P440_FEXE2]>,
  545. InstrStage<1, [P440_FEXE3]>,
  546. InstrStage<1, [P440_FEXE4]>,
  547. InstrStage<1, [P440_FEXE5]>,
  548. InstrStage<1, [P440_FEXE6]>,
  549. InstrStage<13, [P440_FWB]>],
  550. [19, 0, 0],
  551. [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
  552. InstrItinData<IIC_FPFused, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  553. InstrStage<1, [P440_FRACC]>,
  554. InstrStage<1, [P440_FEXE1]>,
  555. InstrStage<1, [P440_FEXE2]>,
  556. InstrStage<1, [P440_FEXE3]>,
  557. InstrStage<1, [P440_FEXE4]>,
  558. InstrStage<1, [P440_FEXE5]>,
  559. InstrStage<1, [P440_FEXE6]>,
  560. InstrStage<1, [P440_FWB]>],
  561. [6, 0, 0, 0],
  562. [P440_FPR_Bypass,
  563. P440_FPR_Bypass, P440_FPR_Bypass,
  564. P440_FPR_Bypass]>,
  565. InstrItinData<IIC_FPRes, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
  566. InstrStage<1, [P440_FRACC]>,
  567. InstrStage<1, [P440_FEXE1]>,
  568. InstrStage<1, [P440_FEXE2]>,
  569. InstrStage<1, [P440_FEXE3]>,
  570. InstrStage<1, [P440_FEXE4]>,
  571. InstrStage<1, [P440_FEXE5]>,
  572. InstrStage<1, [P440_FEXE6]>,
  573. InstrStage<1, [P440_FWB]>],
  574. [6, 0],
  575. [P440_FPR_Bypass, P440_FPR_Bypass]>
  576. ]>;
  577. // ===---------------------------------------------------------------------===//
  578. // PPC440 machine model for scheduling and other instruction cost heuristics.
  579. def PPC440Model : SchedMachineModel {
  580. let IssueWidth = 2; // 2 instructions are dispatched per cycle.
  581. let LoadLatency = 5; // Optimistic load latency assuming bypass.
  582. // This is overriden by OperandCycles if the
  583. // Itineraries are queried instead.
  584. let CompleteModel = 0;
  585. let Itineraries = PPC440Itineraries;
  586. }