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AArch64SchedA57.td

AArch64SchedA57.td 36 KB
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  1. //=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
    2. 

  2. //
    3. 

  3. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
    4. 

  4. // See https://llvm.org/LICENSE.txt for license information.
    5. 

  5. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
    6. 

  6. //
    7. 

  7. //===----------------------------------------------------------------------===//
    8. 

  8. //
    9. 

  9. // This file defines the machine model for ARM Cortex-A57 to support
    10. 

  10. // instruction scheduling and other instruction cost heuristics.
    11. 

  11. //
    12. 

  12. //===----------------------------------------------------------------------===//
    13. 

  13. 

  14. //===----------------------------------------------------------------------===//
    15. 

  15. // The Cortex-A57 is a traditional superscalar microprocessor with a
    16. 

  16. // conservative 3-wide in-order stage for decode and dispatch. Combined with the
    17. 

  17. // much wider out-of-order issue stage, this produced a need to carefully
    18. 

  18. // schedule micro-ops so that all three decoded each cycle are successfully
    19. 

  19. // issued as the reservation station(s) simply don't stay occupied for long.
    20. 

  20. // Therefore, IssueWidth is set to the narrower of the two at three, while still
    21. 

  21. // modeling the machine as out-of-order.
    22. 

  22. 

  23. def CortexA57Model : SchedMachineModel {
    24. 

  24.   let IssueWidth        =   3; // 3-way decode and dispatch
    25. 

  25.   let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
    26. 

  26.   let LoadLatency       =   4; // Optimistic load latency
    27. 

  27.   let MispredictPenalty =  14; // Fetch + Decode/Rename/Dispatch + Branch
    28. 

  28. 

  29.   // Enable partial & runtime unrolling. The magic number is chosen based on
    30. 

  30.   // experiments and benchmarking data.
    31. 

  31.   let LoopMicroOpBufferSize = 16;
    32. 

  32.   let CompleteModel = 1;
    33. 

  33. 

  34.   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
    35. 

  35.                                                     PAUnsupported.F,
    36. 

  36.                                                     SMEUnsupported.F);
    37. 

  37. }
    38. 

  38. 

  39. //===----------------------------------------------------------------------===//
    40. 

  40. // Define each kind of processor resource and number available on Cortex-A57.
    41. 

  41. // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
    42. 

  42. // micro-ops wait for their operands and then issue out-of-order.
    43. 

  43. 

  44. def A57UnitB : ProcResource<1>;  // Type B micro-ops
    45. 

  45. def A57UnitI : ProcResource<2>;  // Type I micro-ops
    46. 

  46. def A57UnitM : ProcResource<1>;  // Type M micro-ops
    47. 

  47. def A57UnitL : ProcResource<1>;  // Type L micro-ops
    48. 

  48. def A57UnitS : ProcResource<1>;  // Type S micro-ops
    49. 

  49. def A57UnitX : ProcResource<1>;  // Type X micro-ops
    50. 

  50. def A57UnitW : ProcResource<1>;  // Type W micro-ops
    51. 

  51. let SchedModel = CortexA57Model in {
    52. 

  52.   def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>;    // Type V micro-ops
    53. 

  53. }
    54. 

  54. 

  55. let SchedModel = CortexA57Model in {
    56. 

  56. 

  57. //===----------------------------------------------------------------------===//
    58. 

  58. // Define customized scheduler read/write types specific to the Cortex-A57.
    59. 

  59. 

  60. include "AArch64SchedA57WriteRes.td"
    61. 

  61. 

  62. //===----------------------------------------------------------------------===//
    63. 

  63. // Map the target-defined scheduler read/write resources and latency for
    64. 

  64. // Cortex-A57. The Cortex-A57 types are directly associated with resources, so
    65. 

  65. // defining the aliases precludes the need for mapping them using WriteRes. The
    66. 

  66. // aliases are sufficient for creating a coarse, working model. As the model
    67. 

  67. // evolves, InstRWs will be used to override some of these SchedAliases.
    68. 

  68. //
    69. 

  69. // WARNING: Using SchedAliases is convenient and works well for latency and
    70. 

  70. //          resource lookup for instructions. However, this creates an entry in
    71. 

  71. //          AArch64WriteLatencyTable with a WriteResourceID of 0, breaking
    72. 

  72. //          any SchedReadAdvance since the lookup will fail.
    73. 

  73. 

  74. def : SchedAlias<WriteImm,   A57Write_1cyc_1I>;
    75. 

  75. def : SchedAlias<WriteI,     A57Write_1cyc_1I>;
    76. 

  76. def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
    77. 

  77. def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
    78. 

  78. def : SchedAlias<WriteExtr,  A57Write_1cyc_1I>;
    79. 

  79. def : SchedAlias<WriteIS,    A57Write_1cyc_1I>;
    80. 

  80. def : SchedAlias<WriteID32,  A57Write_19cyc_1M>;
    81. 

  81. def : SchedAlias<WriteID64,  A57Write_35cyc_1M>;
    82. 

  82. def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; }
    83. 

  83. def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; }
    84. 

  84. def : SchedAlias<WriteBr,    A57Write_1cyc_1B>;
    85. 

  85. def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
    86. 

  86. def : SchedAlias<WriteLD,    A57Write_4cyc_1L>;
    87. 

  87. def : SchedAlias<WriteST,    A57Write_1cyc_1S>;
    88. 

  88. def : SchedAlias<WriteSTP,   A57Write_1cyc_1S>;
    89. 

  89. def : SchedAlias<WriteAdr,   A57Write_1cyc_1I>;
    90. 

  90. def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
    91. 

  91. def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;
    92. 

  92. def : SchedAlias<WriteF,     A57Write_3cyc_1V>;
    93. 

  93. def : SchedAlias<WriteFCmp,  A57Write_3cyc_1V>;
    94. 

  94. def : SchedAlias<WriteFCvt,  A57Write_5cyc_1V>;
    95. 

  95. def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>;
    96. 

  96. def : SchedAlias<WriteFImm,  A57Write_3cyc_1V>;
    97. 

  97. def : WriteRes<WriteFMul, [A57UnitV]> { let Latency = 5;}
    98. 

  98. def : SchedAlias<WriteFDiv,  A57Write_17cyc_1W>;
    99. 

  99. def : SchedAlias<WriteVd,    A57Write_3cyc_1V>;
    100. 

  100. def : SchedAlias<WriteVq,    A57Write_3cyc_1V>;
    101. 

  101. def : SchedAlias<WriteVLD,   A57Write_5cyc_1L>;
    102. 

  102. def : SchedAlias<WriteVST,   A57Write_1cyc_1S>;
    103. 

  103. 

  104. def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
    105. 

  105. 

  106. def : WriteRes<WriteSys,     []> { let Latency = 1; }
    107. 

  107. def : WriteRes<WriteBarrier, []> { let Latency = 1; }
    108. 

  108. def : WriteRes<WriteHint,    []> { let Latency = 1; }
    109. 

  109. 

  110. def : WriteRes<WriteLDHi,    []> { let Latency = 4; }
    111. 

  111. 

  112. // Forwarding logic is only modeled for multiply and accumulate
    113. 

  113. def : ReadAdvance<ReadI,       0>;
    114. 

  114. def : ReadAdvance<ReadISReg,   0>;
    115. 

  115. def : ReadAdvance<ReadIEReg,   0>;
    116. 

  116. def : ReadAdvance<ReadIM,      0>;
    117. 

  117. def : ReadAdvance<ReadIMA,     2, [WriteIM32, WriteIM64]>;
    118. 

  118. def : ReadAdvance<ReadID,      0>;
    119. 

  119. def : ReadAdvance<ReadExtrHi,  0>;
    120. 

  120. def : ReadAdvance<ReadST,      0>;
    121. 

  121. def : ReadAdvance<ReadAdrBase, 0>;
    122. 

  122. def : ReadAdvance<ReadVLD,     0>;
    123. 

  123. 

  124. 

  125. //===----------------------------------------------------------------------===//
    126. 

  126. // Specialize the coarse model by associating instruction groups with the
    127. 

  127. // subtarget-defined types. As the modeled is refined, this will override most
    128. 

  128. // of the above ShchedAlias mappings.
    129. 

  129. 

  130. // Miscellaneous
    131. 

  131. // -----------------------------------------------------------------------------
    132. 

  132. 

  133. def : InstRW<[WriteI], (instrs COPY)>;
    134. 

  134. 

  135. 

  136. // Branch Instructions
    137. 

  137. // -----------------------------------------------------------------------------
    138. 

  138. 

  139. def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
    140. 

  140. def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
    141. 

  141. 

  142. 

  143. // Shifted Register with Shift == 0
    144. 

  144. // ----------------------------------------------------------------------------
    145. 

  145. 

  146. def A57WriteISReg : SchedWriteVariant<[
    147. 

  147.        SchedVar<RegShiftedPred, [WriteISReg]>,
    148. 

  148.        SchedVar<NoSchedPred, [WriteI]>]>;
    149. 

  149. def : InstRW<[A57WriteISReg], (instregex ".*rs$")>;
    150. 

  150. 

  151. 

  152. // Divide and Multiply Instructions
    153. 

  153. // -----------------------------------------------------------------------------
    154. 

  154. 

  155. // Multiply high
    156. 

  156. def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
    157. 

  157. 

  158. 

  159. // Miscellaneous Data-Processing Instructions
    160. 

  160. // -----------------------------------------------------------------------------
    161. 

  161. 

  162. def : InstRW<[A57Write_1cyc_1I],    (instrs EXTRWrri)>;
    163. 

  163. def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
    164. 

  164. def : InstRW<[A57Write_2cyc_1M],    (instregex "BFM")>;
    165. 

  165. 

  166. 

  167. // Cryptography Extensions
    168. 

  168. // -----------------------------------------------------------------------------
    169. 

  169. 

  170. def A57ReadAES  : SchedReadAdvance<3, [A57Write_3cyc_1W]>;
    171. 

  171. def : InstRW<[A57Write_3cyc_1W], (instregex "^AES[DE]")>;
    172. 

  172. def : InstRW<[A57Write_3cyc_1W, A57ReadAES], (instregex "^AESI?MC")>;
    173. 

  173. def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>;
    174. 

  174. def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>;
    175. 

  175. def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>;
    176. 

  176. def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>;
    177. 

  177. def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>;
    178. 

  178. def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>;
    179. 

  179. 

  180. 

  181. // Vector Load
    182. 

  182. // -----------------------------------------------------------------------------
    183. 

  183. 

  184. def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1i(8|16|32)$")>;
    185. 

  185. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
    186. 

  186. def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1i(64)$")>;
    187. 

  187. def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1i(64)_POST$")>;
    188. 

  188. 

  189. def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(8b|4h|2s)$")>;
    190. 

  190. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
    191. 

  191. def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1Rv(1d)$")>;
    192. 

  192. def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1Rv(1d)_POST$")>;
    193. 

  193. def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(16b|8h|4s|2d)$")>;
    194. 

  194. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
    195. 

  195. 

  196. def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(8b|4h|2s|1d)$")>;
    197. 

  197. def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
    198. 

  198. def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(16b|8h|4s|2d)$")>;
    199. 

  199. def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
    200. 

  200. def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Twov(8b|4h|2s|1d)$")>;
    201. 

  201. def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
    202. 

  202. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Twov(16b|8h|4s|2d)$")>;
    203. 

  203. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
    204. 

  204. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Threev(8b|4h|2s|1d)$")>;
    205. 

  205. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
    206. 

  206. def : InstRW<[A57Write_7cyc_3L],            (instregex "LD1Threev(16b|8h|4s|2d)$")>;
    207. 

  207. def : InstRW<[A57Write_7cyc_3L, WriteAdr],  (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
    208. 

  208. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
    209. 

  209. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
    210. 

  210. def : InstRW<[A57Write_8cyc_4L],           (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
    211. 

  211. def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
    212. 

  212. 

  213. def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2i(8|16)$")>;
    214. 

  214. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>;
    215. 

  215. def : InstRW<[A57Write_6cyc_2L],            (instregex "LD2i(32)$")>;
    216. 

  216. def : InstRW<[A57Write_6cyc_2L, WriteAdr],  (instregex "LD2i(32)_POST$")>;
    217. 

  217. def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2i(64)$")>;
    218. 

  218. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2i(64)_POST$")>;
    219. 

  219. 

  220. def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2Rv(8b|4h|2s)$")>;
    221. 

  221. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2Rv(8b|4h|2s)_POST$")>;
    222. 

  222. def : InstRW<[A57Write_5cyc_1L],             (instregex "LD2Rv(1d)$")>;
    223. 

  223. def : InstRW<[A57Write_5cyc_1L, WriteAdr],   (instregex "LD2Rv(1d)_POST$")>;
    224. 

  224. def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2Rv(16b|8h|4s|2d)$")>;
    225. 

  225. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
    226. 

  226. 

  227. def : InstRW<[A57Write_8cyc_1L_1V],             (instregex "LD2Twov(8b|4h|2s)$")>;
    228. 

  228. def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],   (instregex "LD2Twov(8b|4h|2s)_POST$")>;
    229. 

  229. def : InstRW<[A57Write_9cyc_2L_2V],           (instregex "LD2Twov(16b|8h|4s)$")>;
    230. 

  230. def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
    231. 

  231. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD2Twov(2d)$")>;
    232. 

  232. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD2Twov(2d)_POST$")>;
    233. 

  233. 

  234. def : InstRW<[A57Write_9cyc_1L_3V],           (instregex "LD3i(8|16)$")>;
    235. 

  235. def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>;
    236. 

  236. def : InstRW<[A57Write_8cyc_1L_2V],            (instregex "LD3i(32)$")>;
    237. 

  237. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],  (instregex "LD3i(32)_POST$")>;
    238. 

  238. def : InstRW<[A57Write_6cyc_2L],             (instregex "LD3i(64)$")>;
    239. 

  239. def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD3i(64)_POST$")>;
    240. 

  240. 

  241. def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD3Rv(8b|4h|2s)$")>;
    242. 

  242. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD3Rv(8b|4h|2s)_POST$")>;
    243. 

  243. def : InstRW<[A57Write_6cyc_2L],              (instregex "LD3Rv(1d)$")>;
    244. 

  244. def : InstRW<[A57Write_6cyc_2L, WriteAdr],    (instregex "LD3Rv(1d)_POST$")>;
    245. 

  245. def : InstRW<[A57Write_9cyc_1L_3V],            (instregex "LD3Rv(16b|8h|4s)$")>;
    246. 

  246. def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr],  (instregex "LD3Rv(16b|8h|4s)_POST$")>;
    247. 

  247. def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD3Rv(2d)$")>;
    248. 

  248. def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
    249. 

  249. 

  250. def : InstRW<[A57Write_9cyc_2L_2V],               (instregex "LD3Threev(8b|4h|2s)$")>;
    251. 

  251. def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],     (instregex "LD3Threev(8b|4h|2s)_POST$")>;
    252. 

  252. def : InstRW<[A57Write_10cyc_3L_4V],           (instregex "LD3Threev(16b|8h|4s)$")>;
    253. 

  253. def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
    254. 

  254. def : InstRW<[A57Write_8cyc_4L],               (instregex "LD3Threev(2d)$")>;
    255. 

  255. def : InstRW<[A57Write_8cyc_4L, WriteAdr],     (instregex "LD3Threev(2d)_POST$")>;
    256. 

  256. 

  257. def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(8|16)$")>;
    258. 

  258. def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>;
    259. 

  259. def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD4i(32)$")>;
    260. 

  260. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD4i(32)_POST$")>;
    261. 

  261. def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(64)$")>;
    262. 

  262. def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>;
    263. 

  263. 

  264. def : InstRW<[A57Write_8cyc_1L_2V],              (instregex "LD4Rv(8b|4h|2s)$")>;
    265. 

  265. def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],    (instregex "LD4Rv(8b|4h|2s)_POST$")>;
    266. 

  266. def : InstRW<[A57Write_6cyc_2L],               (instregex "LD4Rv(1d)$")>;
    267. 

  267. def : InstRW<[A57Write_6cyc_2L, WriteAdr],     (instregex "LD4Rv(1d)_POST$")>;
    268. 

  268. def : InstRW<[A57Write_9cyc_2L_3V],            (instregex "LD4Rv(16b|8h|4s)$")>;
    269. 

  269. def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr],  (instregex "LD4Rv(16b|8h|4s)_POST$")>;
    270. 

  270. def : InstRW<[A57Write_9cyc_2L_4V],           (instregex "LD4Rv(2d)$")>;
    271. 

  271. def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
    272. 

  272. 

  273. def : InstRW<[A57Write_9cyc_2L_2V],                (instregex "LD4Fourv(8b|4h|2s)$")>;
    274. 

  274. def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],      (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
    275. 

  275. def : InstRW<[A57Write_11cyc_4L_4V],           (instregex "LD4Fourv(16b|8h|4s)$")>;
    276. 

  276. def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
    277. 

  277. def : InstRW<[A57Write_8cyc_4L],                (instregex "LD4Fourv(2d)$")>;
    278. 

  278. def : InstRW<[A57Write_8cyc_4L, WriteAdr],      (instregex "LD4Fourv(2d)_POST$")>;
    279. 

  279. 

  280. // Vector Store
    281. 

  281. // -----------------------------------------------------------------------------
    282. 

  282. 

  283. def : InstRW<[A57Write_1cyc_1S],            (instregex "ST1i(8|16|32)$")>;
    284. 

  284. def : InstRW<[A57Write_1cyc_1S, WriteAdr],  (instregex "ST1i(8|16|32)_POST$")>;
    285. 

  285. def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST1i(64)$")>;
    286. 

  286. def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>;
    287. 

  287. 

  288. def : InstRW<[A57Write_1cyc_1S],                  (instregex "ST1Onev(8b|4h|2s|1d)$")>;
    289. 

  289. def : InstRW<[A57Write_1cyc_1S, WriteAdr],        (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
    290. 

  290. def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Onev(16b|8h|4s|2d)$")>;
    291. 

  291. def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
    292. 

  292. def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Twov(8b|4h|2s|1d)$")>;
    293. 

  293. def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
    294. 

  294. def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Twov(16b|8h|4s|2d)$")>;
    295. 

  295. def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
    296. 

  296. def : InstRW<[A57Write_3cyc_3S],                (instregex "ST1Threev(8b|4h|2s|1d)$")>;
    297. 

  297. def : InstRW<[A57Write_3cyc_3S, WriteAdr],      (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
    298. 

  298. def : InstRW<[A57Write_6cyc_6S],             (instregex "ST1Threev(16b|8h|4s|2d)$")>;
    299. 

  299. def : InstRW<[A57Write_6cyc_6S, WriteAdr],   (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
    300. 

  300. def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
    301. 

  301. def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
    302. 

  302. def : InstRW<[A57Write_8cyc_8S],           (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
    303. 

  303. def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
    304. 

  304. 

  305. def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST2i(8|16|32)$")>;
    306. 

  306. def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
    307. 

  307. def : InstRW<[A57Write_2cyc_2S],           (instregex "ST2i(64)$")>;
    308. 

  308. def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>;
    309. 

  309. 

  310. def : InstRW<[A57Write_3cyc_2S_1V],              (instregex "ST2Twov(8b|4h|2s)$")>;
    311. 

  311. def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST$")>;
    312. 

  312. def : InstRW<[A57Write_4cyc_4S_2V],           (instregex "ST2Twov(16b|8h|4s)$")>;
    313. 

  313. def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
    314. 

  314. def : InstRW<[A57Write_4cyc_4S],             (instregex "ST2Twov(2d)$")>;
    315. 

  315. def : InstRW<[A57Write_4cyc_4S, WriteAdr],   (instregex "ST2Twov(2d)_POST$")>;
    316. 

  316. 

  317. def : InstRW<[A57Write_3cyc_1S_1V],            (instregex "ST3i(8|16)$")>;
    318. 

  318. def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],  (instregex "ST3i(8|16)_POST$")>;
    319. 

  319. def : InstRW<[A57Write_3cyc_3S],           (instregex "ST3i(32)$")>;
    320. 

  320. def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>;
    321. 

  321. def : InstRW<[A57Write_3cyc_2S_1V],           (instregex "ST3i(64)$")>;
    322. 

  322. def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>;
    323. 

  323. 

  324. def : InstRW<[A57Write_3cyc_3S_2V],                 (instregex "ST3Threev(8b|4h|2s)$")>;
    325. 

  325. def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr],       (instregex "ST3Threev(8b|4h|2s)_POST$")>;
    326. 

  326. def : InstRW<[A57Write_6cyc_6S_4V],           (instregex "ST3Threev(16b|8h|4s)$")>;
    327. 

  327. def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
    328. 

  328. def : InstRW<[A57Write_6cyc_6S],                (instregex "ST3Threev(2d)$")>;
    329. 

  329. def : InstRW<[A57Write_6cyc_6S, WriteAdr],      (instregex "ST3Threev(2d)_POST$")>;
    330. 

  330. 

  331. def : InstRW<[A57Write_3cyc_1S_1V],             (instregex "ST4i(8|16)$")>;
    332. 

  332. def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],   (instregex "ST4i(8|16)_POST$")>;
    333. 

  333. def : InstRW<[A57Write_4cyc_4S],           (instregex "ST4i(32)$")>;
    334. 

  334. def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>;
    335. 

  335. def : InstRW<[A57Write_3cyc_2S_1V],            (instregex "ST4i(64)$")>;
    336. 

  336. def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],  (instregex "ST4i(64)_POST$")>;
    337. 

  337. 

  338. def : InstRW<[A57Write_4cyc_4S_2V],                  (instregex "ST4Fourv(8b|4h|2s)$")>;
    339. 

  339. def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr],        (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
    340. 

  340. def : InstRW<[A57Write_8cyc_8S_4V],           (instregex "ST4Fourv(16b|8h|4s)$")>;
    341. 

  341. def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
    342. 

  342. def : InstRW<[A57Write_8cyc_8S],                (instregex "ST4Fourv(2d)$")>;
    343. 

  343. def : InstRW<[A57Write_8cyc_8S, WriteAdr],      (instregex "ST4Fourv(2d)_POST$")>;
    344. 

  344. 

  345. // Vector - Integer
    346. 

  346. // -----------------------------------------------------------------------------
    347. 

  347. 

  348. // Reference for forms in this group
    349. 

  349. //   D form - v8i8, v4i16, v2i32
    350. 

  350. //   Q form - v16i8, v8i16, v4i32
    351. 

  351. //   D form - v1i8, v1i16, v1i32, v1i64
    352. 

  352. //   Q form - v16i8, v8i16, v4i32, v2i64
    353. 

  353. //   D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
    354. 

  354. //   Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
    355. 

  355. 

  356. // Cortex A57 Software Optimization Guide Sec 3.14
    357. 

  357. // Advance for absolute diff accum, pairwise add and accumulate, shift accumulate
    358. 

  358. def A57ReadIVA3 : SchedReadAdvance<3, [A57Write_4cyc_1X_NonMul_Forward, A57Write_5cyc_2X_NonMul_Forward]>;
    359. 

  359. 

  360. // ASIMD absolute diff accum, D-form
    361. 

  361. def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
    362. 

  362. // ASIMD absolute diff accum, Q-form
    363. 

  363. def : InstRW<[A57Write_5cyc_2X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>;
    364. 

  364. // ASIMD absolute diff accum long
    365. 

  365. def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABAL")>;
    366. 

  366. 

  367. // ASIMD arith, reduce, 4H/4S
    368. 

  368. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
    369. 

  369. // ASIMD arith, reduce, 8B/8H
    370. 

  370. def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
    371. 

  371. // ASIMD arith, reduce, 16B
    372. 

  372. def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>;
    373. 

  373. 

  374. // ASIMD max/min, reduce, 4H/4S
    375. 

  375. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
    376. 

  376. // ASIMD max/min, reduce, 8B/8H
    377. 

  377. def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
    378. 

  378. // ASIMD max/min, reduce, 16B
    379. 

  379. def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>;
    380. 

  380. 

  381. // ASIMD multiply, D-form
    382. 

  382. // MUL
    383. 

  383. def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
    384. 

  384. // PMUL, SQDMULH, SQRDMULH
    385. 

  385. def : InstRW<[A57Write_5cyc_1W], (instregex "^(PMUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
    386. 

  386. 

  387. // ASIMD multiply, Q-form
    388. 

  388. // MUL
    389. 

  389. def : InstRW<[A57Write_6cyc_2W_Mul_Forward], (instregex "^MUL(v16i8|v8i16|v4i32)(_indexed)?$")>;
    390. 

  390. // PMUL, SQDMULH, SQRDMULH
    391. 

  391. def : InstRW<[A57Write_6cyc_2W], (instregex "^(PMUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
    392. 

  392. 

  393. // Cortex A57 Software Optimization Guide Sec 3.14
    394. 

  394. def A57ReadIVMA4   : SchedReadAdvance<4 , [A57Write_5cyc_1W_Mul_Forward, A57Write_6cyc_2W_Mul_Forward]>;
    395. 

  395. def A57ReadIVMA3   : SchedReadAdvance<3 , [A57Write_5cyc_1W_Mul_Forward, A57Write_6cyc_2W_Mul_Forward]>;
    396. 

  396. 

  397. // ASIMD multiply accumulate, D-form
    398. 

  398. def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
    399. 

  399. // ASIMD multiply accumulate, Q-form
    400. 

  400. def : InstRW<[A57Write_6cyc_2W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>;
    401. 

  401. 

  402. // ASIMD multiply accumulate long
    403. 

  403. // ASIMD multiply accumulate saturating long
    404. 

  404. def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA4], (instregex "^(S|U)ML[AS]L")>;
    405. 

  405. def : InstRW<[A57Write_5cyc_1W_Mul_Forward, A57ReadIVMA3], (instregex "^SQDML[AS]L")>;
    406. 

  406. 

  407. // ASIMD multiply long
    408. 

  408. def : InstRW<[A57Write_5cyc_1W_Mul_Forward], (instregex "^(S|U)MULL")>;
    409. 

  409. def : InstRW<[A57Write_5cyc_1W], (instregex "^SQDMULL")>;
    410. 

  410. def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
    411. 

  411. def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>;
    412. 

  412. 

  413. // ASIMD pairwise add and accumulate
    414. 

  414. // ASIMD shift accumulate
    415. 

  415. def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ADALP")>;
    416. 

  416. def : InstRW<[A57Write_4cyc_1X_NonMul_Forward, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>;
    417. 

  417. 

  418. // ASIMD shift by immed, complex
    419. 

  419. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>;
    420. 

  420. def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>;
    421. 

  421. 

  422. 

  423. // ASIMD shift by register, basic, Q-form
    424. 

  424. def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
    425. 

  425. 

  426. // ASIMD shift by register, complex, D-form
    427. 

  427. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
    428. 

  428. 

  429. // ASIMD shift by register, complex, Q-form
    430. 

  430. def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
    431. 

  431. 

  432. 

  433. // Vector - Floating Point
    434. 

  434. // -----------------------------------------------------------------------------
    435. 

  435. 

  436. // Reference for forms in this group
    437. 

  437. //   D form - v2f32
    438. 

  438. //   Q form - v4f32, v2f64
    439. 

  439. //   D form - 32, 64
    440. 

  440. //   D form - v1i32, v1i64
    441. 

  441. //   D form - v2i32
    442. 

  442. //   Q form - v4i32, v2i64
    443. 

  443. 

  444. // ASIMD FP arith, normal, D-form
    445. 

  445. def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
    446. 

  446. // ASIMD FP arith, normal, Q-form
    447. 

  447. def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
    448. 

  448. 

  449. // ASIMD FP arith, pairwise, D-form
    450. 

  450. def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
    451. 

  451. // ASIMD FP arith, pairwise, Q-form
    452. 

  452. def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
    453. 

  453. 

  454. // ASIMD FP compare, D-form
    455. 

  455. def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
    456. 

  456. // ASIMD FP compare, Q-form
    457. 

  457. def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>;
    458. 

  458. 

  459. // ASIMD FP convert, long and narrow
    460. 

  460. def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>;
    461. 

  461. // ASIMD FP convert, other, D-form
    462. 

  462. def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
    463. 

  463. // ASIMD FP convert, other, Q-form
    464. 

  464. def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;
    465. 

  465. 

  466. // ASIMD FP divide, D-form, F32
    467. 

  467. def : InstRW<[A57Write_17cyc_1W], (instregex "FDIVv2f32")>;
    468. 

  468. // ASIMD FP divide, Q-form, F32
    469. 

  469. def : InstRW<[A57Write_34cyc_2W], (instregex "FDIVv4f32")>;
    470. 

  470. // ASIMD FP divide, Q-form, F64
    471. 

  471. def : InstRW<[A57Write_64cyc_2W], (instregex "FDIVv2f64")>;
    472. 

  472. 

  473. // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
    474. 

  474. // ASIMD FP square root, D-form, F32
    475. 

  475. def : InstRW<[A57Write_17cyc_1W], (instregex "FSQRTv2f32")>;
    476. 

  476. // ASIMD FP square root, Q-form, F32
    477. 

  477. def : InstRW<[A57Write_34cyc_2W], (instregex "FSQRTv4f32")>;
    478. 

  478. // ASIMD FP square root, Q-form, F64
    479. 

  479. def : InstRW<[A57Write_64cyc_2W], (instregex "FSQRTv2f64")>;
    480. 

  480. 

  481. // ASIMD FP max/min, normal, D-form
    482. 

  482. def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
    483. 

  483. // ASIMD FP max/min, normal, Q-form
    484. 

  484. def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
    485. 

  485. // ASIMD FP max/min, pairwise, D-form
    486. 

  486. def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
    487. 

  487. // ASIMD FP max/min, pairwise, Q-form
    488. 

  488. def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
    489. 

  489. // ASIMD FP max/min, reduce
    490. 

  490. def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
    491. 

  491. 

  492. // ASIMD FP multiply, D-form, FZ
    493. 

  493. def : InstRW<[A57Write_5cyc_1V_FP_Forward], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
    494. 

  494. // ASIMD FP multiply, Q-form, FZ
    495. 

  495. def : InstRW<[A57Write_5cyc_2V_FP_Forward], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
    496. 

  496. 

  497. // ASIMD FP multiply accumulate, D-form, FZ
    498. 

  498. // ASIMD FP multiply accumulate, Q-form, FZ
    499. 

  499. def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
    500. 

  500. def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10;  }
    501. 

  501. 

  502. // Cortex A57 Software Optimization Guide Sec 3.15
    503. 

  503. // Advances from FP mul and mul-accum to mul-accum
    504. 

  504. def A57ReadFPVMA5  : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ, A57Write_5cyc_1V_FP_Forward, A57Write_5cyc_2V_FP_Forward]>;
    505. 

  505. def A57ReadFPVMA6  : SchedReadAdvance<6, [A57WriteFPVMAD, A57WriteFPVMAQ, A57Write_5cyc_1V_FP_Forward, A57Write_5cyc_2V_FP_Forward]>;
    506. 

  506. 

  507. def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
    508. 

  508. def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA6], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
    509. 

  509. 

  510. // ASIMD FP round, D-form
    511. 

  511. def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
    512. 

  512. // ASIMD FP round, Q-form
    513. 

  513. def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
    514. 

  514. 

  515. 

  516. // Vector - Miscellaneous
    517. 

  517. // -----------------------------------------------------------------------------
    518. 

  518. 

  519. // Reference for forms in this group
    520. 

  520. //   D form - v8i8, v4i16, v2i32
    521. 

  521. //   Q form - v16i8, v8i16, v4i32
    522. 

  522. //   D form - v1i8, v1i16, v1i32, v1i64
    523. 

  523. //   Q form - v16i8, v8i16, v4i32, v2i64
    524. 

  524. 

  525. // ASIMD bitwise insert, Q-form
    526. 

  526. def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL|BSP)v16i8")>;
    527. 

  527. 

  528. // ASIMD duplicate, gen reg, D-form and Q-form
    529. 

  529. def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUP(i8|i16|i32|i64)$")>;
    530. 

  530. def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>;
    531. 

  531. 

  532. // ASIMD move, saturating
    533. 

  533. def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>;
    534. 

  534. 

  535. // ASIMD reciprocal estimate, D-form
    536. 

  536. def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
    537. 

  537. // ASIMD reciprocal estimate, Q-form
    538. 

  538. def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>;
    539. 

  539. 

  540. // ASIMD reciprocal step, D-form, FZ
    541. 

  541. def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>;
    542. 

  542. // ASIMD reciprocal step, Q-form, FZ
    543. 

  543. def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>;
    544. 

  544. 

  545. // ASIMD table lookup, D-form
    546. 

  546. def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>;
    547. 

  547. def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>;
    548. 

  548. def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>;
    549. 

  549. def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>;
    550. 

  550. // ASIMD table lookup, Q-form
    551. 

  551. def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>;
    552. 

  552. def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>;
    553. 

  553. def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>;
    554. 

  554. def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>;
    555. 

  555. 

  556. // ASIMD transfer, element to gen reg
    557. 

  557. def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>;
    558. 

  558. 

  559. // ASIMD transfer, gen reg to element
    560. 

  560. def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>;
    561. 

  561. 

  562. // ASIMD unzip/zip, Q-form
    563. 

  563. def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>;
    564. 

  564. 

  565. 

  566. // Remainder
    567. 

  567. // -----------------------------------------------------------------------------
    568. 

  568. 

  569. def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>;
    570. 

  570. 

  571. // Cortex A57 Software Optimization Guide Sec 3.10
    572. 

  572. def A57WriteFPMA  : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
    573. 

  573. def A57ReadFPMA5  : SchedReadAdvance<5, [A57WriteFPMA, WriteFMul]>;
    574. 

  574. def A57ReadFPM    : SchedReadAdvance<0>;
    575. 

  575. def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
    576. 

  576. 

  577. def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
    578. 

  578. def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>;
    579. 

  579. 

  580. def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>;
    581. 

  581. def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>;
    582. 

  582. 

  583. def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>;
    584. 

  584. 

  585. def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
    586. 

  586. 

  587. def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>;
    588. 

  588. def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>;
    589. 

  589. 

  590. def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>;
    591. 

  591. def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>;
    592. 

  592. def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>;
    593. 

  593. def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>;
    594. 

  594. def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>;
    595. 

  595. def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>;
    596. 

  596. def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>;
    597. 

  597. def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>;
    598. 

  598. def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>;
    599. 

  599. def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>;
    600. 

  600. def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>;
    601. 

  601. def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>;
    602. 

  602. def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>;
    603. 

  603. def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>;
    604. 

  604. def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>;
    605. 

  605. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
    606. 

  606. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>;
    607. 

  607. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>;
    608. 

  608. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>;
    609. 

  609. def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>;
    610. 

  610. def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>;
    611. 

  611. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
    612. 

  612. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>;
    613. 

  613. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>;
    614. 

  614. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>;
    615. 

  615. def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>;
    616. 

  616. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>;
    617. 

  617. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>;
    618. 

  618. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
    619. 

  619. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>;
    620. 

  620. def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>;
    621. 

  621. def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>;
    622. 

  622. def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>;
    623. 

  623. def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>;
    624. 

  624. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
    625. 

  625. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>;
    626. 

  626. def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>;
    627. 

  627. def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>;
    628. 

  628. def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>;
    629. 

  629. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>;
    630. 

  630. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>;
    631. 

  631. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>;
    632. 

  632. def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>;
    633. 

  633. def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>;
    634. 

  634. def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
    635. 

  635. def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>;
    636. 

  636. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>;
    637. 

  637. def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>;
    638. 

  638. def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>;
    639. 

  639. def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>;
    640. 

  640. def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>;
    641. 

  641. def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>;
    642. 

  642. def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>;
    643. 

  643. def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>;
    644. 

  644. 

  645. def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>;
    646. 

  646. def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>;
    647. 

  647. def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>;
    648. 

  648. def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>;
    649. 

  649. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>;
    650. 

  650. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>;
    651. 

  651. def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>;
    652. 

  652. def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>;
    653. 

  653. def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>;
    654. 

  654. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>;
    655. 

  655. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>;
    656. 

  656. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>;
    657. 

  657. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>;
    658. 

  658. def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>;
    659. 

  659. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>;
    660. 

  660. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>;
    661. 

  661. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>;
    662. 

  662. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>;
    663. 

  663. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>;
    664. 

  664. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>;
    665. 

  665. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>;
    666. 

  666. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>;
    667. 

  667. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>;
    668. 

  668. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>;
    669. 

  669. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>;
    670. 

  670. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>;
    671. 

  671. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>;
    672. 

  672. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>;
    673. 

  673. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>;
    674. 

  674. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>;
    675. 

  675. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>;
    676. 

  676. def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>;
    677. 

  677. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>;
    678. 

  678. def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>;
    679. 

  679. def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>;
    680. 

  680. def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>;
    681. 

  681. def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>;
    682. 

  682. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>;
    683. 

  683. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>;
    684. 

  684. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>;
    685. 

  685. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>;
    686. 

  686. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>;
    687. 

  687. def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>;
    688. 

  688. def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>;
    689. 

  689. 

  690. } // SchedModel = CortexA57Model
    691.