validate canons without yatest_common

certs/yandex_internal.pem

@@ -0,0 +1,62 @@
+-----BEGIN CERTIFICATE-----
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+RjFWthiFK45+TZRHAcsG9JuV8JNvgoKaL75v/GUsKaeJ3Cps3rBStfc=
+-----END CERTIFICATE-----
+-----BEGIN CERTIFICATE-----
+MIIFGTCCAwGgAwIBAgIQJMM7ZIy2SYxCBgK7WcFwnjANBgkqhkiG9w0BAQ0FADAf
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+LpuQKbSbIERsmR+QqQ==
+-----END CERTIFICATE-----
+

contrib/libs/cxxsupp/libcxx/include/experimental/functional

@@ -0,0 +1,425 @@
+// -*- C++ -*-
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _LIBCPP_EXPERIMENTAL_FUNCTIONAL
+#define _LIBCPP_EXPERIMENTAL_FUNCTIONAL
+
+/*
+   experimental/functional synopsis
+
+#include <algorithm>
+
+namespace std {
+namespace experimental {
+inline namespace fundamentals_v1 {
+    // 4.3, Searchers
+    template<class ForwardIterator, class BinaryPredicate = equal_to<>>
+      class default_searcher;
+
+    template<class RandomAccessIterator,
+             class Hash = hash<typename iterator_traits<RandomAccessIterator>::value_type>,
+             class BinaryPredicate = equal_to<>>
+      class boyer_moore_searcher;
+
+    template<class RandomAccessIterator,
+             class Hash = hash<typename iterator_traits<RandomAccessIterator>::value_type>,
+             class BinaryPredicate = equal_to<>>
+      class boyer_moore_horspool_searcher;
+
+    template<class ForwardIterator, class BinaryPredicate = equal_to<>>
+    default_searcher<ForwardIterator, BinaryPredicate>
+    make_default_searcher(ForwardIterator pat_first, ForwardIterator pat_last,
+                          BinaryPredicate pred = BinaryPredicate());
+
+    template<class RandomAccessIterator,
+             class Hash = hash<typename iterator_traits<RandomAccessIterator>::value_type>,
+             class BinaryPredicate = equal_to<>>
+    boyer_moore_searcher<RandomAccessIterator, Hash, BinaryPredicate>
+    make_boyer_moore_searcher(
+        RandomAccessIterator pat_first, RandomAccessIterator pat_last,
+        Hash hf = Hash(), BinaryPredicate pred = BinaryPredicate());
+
+    template<class RandomAccessIterator,
+             class Hash = hash<typename iterator_traits<RandomAccessIterator>::value_type>,
+             class BinaryPredicate = equal_to<>>
+    boyer_moore_horspool_searcher<RandomAccessIterator, Hash, BinaryPredicate>
+    make_boyer_moore_horspool_searcher(
+        RandomAccessIterator pat_first, RandomAccessIterator pat_last,
+        Hash hf = Hash(), BinaryPredicate pred = BinaryPredicate());
+
+  } // namespace fundamentals_v1
+  } // namespace experimental
+
+} // namespace std
+
+*/
+
+#include <__debug>
+#include <__memory/uses_allocator.h>
+#include <array>
+#include <experimental/__config>
+#include <functional>
+#include <type_traits>
+#include <unordered_map>
+#include <vector>
+
+#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
+#  pragma GCC system_header
+#endif
+
+_LIBCPP_PUSH_MACROS
+#include <__undef_macros>
+
+_LIBCPP_BEGIN_NAMESPACE_LFTS
+
+#if _LIBCPP_STD_VER > 11
+// default searcher
+template<class _ForwardIterator, class _BinaryPredicate = equal_to<>>
+class _LIBCPP_TEMPLATE_VIS default_searcher {
+public:
+    _LIBCPP_INLINE_VISIBILITY
+    default_searcher(_ForwardIterator __f, _ForwardIterator __l,
+                       _BinaryPredicate __p = _BinaryPredicate())
+        : __first_(__f), __last_(__l), __pred_(__p) {}
+
+    template <typename _ForwardIterator2>
+    _LIBCPP_INLINE_VISIBILITY
+    pair<_ForwardIterator2, _ForwardIterator2>
+    operator () (_ForwardIterator2 __f, _ForwardIterator2 __l) const
+    {
+        return _VSTD::__search(__f, __l, __first_, __last_, __pred_,
+            typename iterator_traits<_ForwardIterator>::iterator_category(),
+            typename iterator_traits<_ForwardIterator2>::iterator_category());
+    }
+
+private:
+    _ForwardIterator __first_;
+    _ForwardIterator __last_;
+    _BinaryPredicate __pred_;
+    };
+
+template<class _ForwardIterator, class _BinaryPredicate = equal_to<>>
+_LIBCPP_INLINE_VISIBILITY
+default_searcher<_ForwardIterator, _BinaryPredicate>
+make_default_searcher( _ForwardIterator __f, _ForwardIterator __l, _BinaryPredicate __p = _BinaryPredicate ())
+{
+    return default_searcher<_ForwardIterator, _BinaryPredicate>(__f, __l, __p);
+}
+
+template<class _Key, class _Value, class _Hash, class _BinaryPredicate, bool /*useArray*/> class _BMSkipTable;
+
+//  General case for BM data searching; use a map
+template<class _Key, typename _Value, class _Hash, class _BinaryPredicate>
+class _BMSkipTable<_Key, _Value, _Hash, _BinaryPredicate, false> {
+    typedef _Value value_type;
+    typedef _Key   key_type;
+
+    const _Value __default_value_;
+    std::unordered_map<_Key, _Value, _Hash, _BinaryPredicate> __table;
+
+public:
+    _LIBCPP_INLINE_VISIBILITY
+    _BMSkipTable(size_t __sz, _Value __default, _Hash __hf, _BinaryPredicate __pred)
+        : __default_value_(__default), __table(__sz, __hf, __pred) {}
+
+    _LIBCPP_INLINE_VISIBILITY
+    void insert(const key_type &__key, value_type __val)
+    {
+        __table [__key] = __val;    // Would skip_.insert (val) be better here?
+    }
+
+    _LIBCPP_INLINE_VISIBILITY
+    value_type operator [](const key_type & __key) const
+    {
+        auto __it = __table.find (__key);
+        return __it == __table.end() ? __default_value_ : __it->second;
+    }
+};
+
+
+//  Special case small numeric values; use an array
+template<class _Key, typename _Value, class _Hash, class _BinaryPredicate>
+class _BMSkipTable<_Key, _Value, _Hash, _BinaryPredicate, true> {
+private:
+    typedef _Value value_type;
+    typedef _Key   key_type;
+
+    typedef typename make_unsigned<key_type>::type unsigned_key_type;
+    typedef std::array<value_type, numeric_limits<unsigned_key_type>::max()> skip_map;
+    skip_map __table;
+
+public:
+    _LIBCPP_INLINE_VISIBILITY
+    _BMSkipTable(size_t /*__sz*/, _Value __default, _Hash /*__hf*/, _BinaryPredicate /*__pred*/)
+    {
+        std::fill_n(__table.begin(), __table.size(), __default);
+    }
+
+    _LIBCPP_INLINE_VISIBILITY
+    void insert(key_type __key, value_type __val)
+    {
+        __table[static_cast<unsigned_key_type>(__key)] = __val;
+    }
+
+    _LIBCPP_INLINE_VISIBILITY
+    value_type operator [](key_type __key) const
+    {
+        return __table[static_cast<unsigned_key_type>(__key)];
+    }
+};
+
+
+template <class _RandomAccessIterator1,
+          class _Hash = hash<typename iterator_traits<_RandomAccessIterator1>::value_type>,
+          class _BinaryPredicate = equal_to<>>
+class _LIBCPP_TEMPLATE_VIS boyer_moore_searcher {
+private:
+    typedef typename std::iterator_traits<_RandomAccessIterator1>::difference_type difference_type;
+    typedef typename std::iterator_traits<_RandomAccessIterator1>::value_type      value_type;
+    typedef _BMSkipTable<value_type, difference_type, _Hash, _BinaryPredicate,
+                    is_integral<value_type>::value && // what about enums?
+                    sizeof(value_type) == 1 &&
+                    is_same<_Hash, hash<value_type>>::value &&
+                    is_same<_BinaryPredicate, equal_to<>>::value
+            > skip_table_type;
+
+public:
+    boyer_moore_searcher(_RandomAccessIterator1 __f, _RandomAccessIterator1 __l,
+                _Hash __hf = _Hash(), _BinaryPredicate __pred = _BinaryPredicate())
+            : __first_(__f), __last_(__l), __pred_(__pred),
+              __pattern_length_(_VSTD::distance(__first_, __last_)),
+              __skip_{make_shared<skip_table_type>(__pattern_length_, -1, __hf, __pred_)},
+              __suffix_{make_shared<vector<difference_type>>(__pattern_length_ + 1)}
+        {
+    //  build the skip table
+        for ( difference_type __i = 0; __f != __l; ++__f, (void) ++__i )
+            __skip_->insert(*__f, __i);
+
+        this->__build_suffix_table ( __first_, __last_, __pred_ );
+        }
+
+    template <typename _RandomAccessIterator2>
+    pair<_RandomAccessIterator2, _RandomAccessIterator2>
+    operator ()(_RandomAccessIterator2 __f, _RandomAccessIterator2 __l) const
+    {
+        static_assert(__is_same_uncvref<typename iterator_traits<_RandomAccessIterator1>::value_type,
+                                        typename iterator_traits<_RandomAccessIterator2>::value_type>::value,
+                      "Corpus and Pattern iterators must point to the same type");
+
+        if (__f      == __l )    return make_pair(__l, __l); // empty corpus
+        if (__first_ == __last_) return make_pair(__f, __f); // empty pattern
+
+    //  If the pattern is larger than the corpus, we can't find it!
+        if ( __pattern_length_ > _VSTD::distance(__f, __l))
+            return make_pair(__l, __l);
+
+    //  Do the search
+        return this->__search(__f, __l);
+    }
+
+private:
+    _RandomAccessIterator1               __first_;
+    _RandomAccessIterator1               __last_;
+    _BinaryPredicate                     __pred_;
+    difference_type                      __pattern_length_;
+    shared_ptr<skip_table_type>          __skip_;
+    shared_ptr<vector<difference_type>>  __suffix_;
+
+    template <typename _RandomAccessIterator2>
+    pair<_RandomAccessIterator2, _RandomAccessIterator2>
+    __search(_RandomAccessIterator2 __f, _RandomAccessIterator2 __l) const
+    {
+        _RandomAccessIterator2 __cur = __f;
+        const _RandomAccessIterator2 __last = __l - __pattern_length_;
+        const skip_table_type &         __skip   = *__skip_.get();
+        const vector<difference_type> & __suffix = *__suffix_.get();
+
+        while (__cur <= __last)
+        {
+
+        //  Do we match right where we are?
+            difference_type __j = __pattern_length_;
+            while (__pred_(__first_ [__j-1], __cur [__j-1])) {
+                __j--;
+            //  We matched - we're done!
+                if ( __j == 0 )
+                    return make_pair(__cur, __cur + __pattern_length_);
+                }
+
+        //  Since we didn't match, figure out how far to skip forward
+            difference_type __k = __skip[__cur [ __j - 1 ]];
+            difference_type __m = __j - __k - 1;
+            if (__k < __j && __m > __suffix[ __j ])
+                __cur += __m;
+            else
+                __cur += __suffix[ __j ];
+        }
+
+        return make_pair(__l, __l);     // We didn't find anything
+    }
+
+
+    template<typename _Iterator, typename _Container>
+    void __compute_bm_prefix ( _Iterator __f, _Iterator __l, _BinaryPredicate __pred, _Container &__prefix )
+    {
+        const size_t __count = _VSTD::distance(__f, __l);
+
+        __prefix[0] = 0;
+        size_t __k = 0;
+        for ( size_t __i = 1; __i < __count; ++__i )
+        {
+            while ( __k > 0 && !__pred ( __f[__k], __f[__i] ))
+                __k = __prefix [ __k - 1 ];
+
+            if ( __pred ( __f[__k], __f[__i] ))
+                __k++;
+            __prefix [ __i ] = __k;
+        }
+    }
+
+    void __build_suffix_table(_RandomAccessIterator1 __f, _RandomAccessIterator1 __l,
+                                                    _BinaryPredicate __pred)
+    {
+        const size_t __count = _VSTD::distance(__f, __l);
+        vector<difference_type> & __suffix = *__suffix_.get();
+        if (__count > 0)
+        {
+            vector<value_type> __scratch(__count);
+
+            __compute_bm_prefix(__f, __l, __pred, __scratch);
+            for ( size_t __i = 0; __i <= __count; __i++ )
+                __suffix[__i] = __count - __scratch[__count-1];
+
+            typedef reverse_iterator<_RandomAccessIterator1> _RevIter;
+            __compute_bm_prefix(_RevIter(__l), _RevIter(__f), __pred, __scratch);
+
+            for ( size_t __i = 0; __i < __count; __i++ )
+            {
+                const size_t     __j = __count - __scratch[__i];
+                const difference_type __k = __i     - __scratch[__i] + 1;
+
+                if (__suffix[__j] > __k)
+                    __suffix[__j] = __k;
+            }
+        }
+    }
+
+};
+
+template<class _RandomAccessIterator,
+         class _Hash = hash<typename iterator_traits<_RandomAccessIterator>::value_type>,
+         class _BinaryPredicate = equal_to<>>
+_LIBCPP_INLINE_VISIBILITY
+boyer_moore_searcher<_RandomAccessIterator, _Hash, _BinaryPredicate>
+make_boyer_moore_searcher( _RandomAccessIterator __f, _RandomAccessIterator __l,
+                    _Hash __hf = _Hash(), _BinaryPredicate __p = _BinaryPredicate ())
+{
+    return boyer_moore_searcher<_RandomAccessIterator, _Hash, _BinaryPredicate>(__f, __l, __hf, __p);
+}
+
+// boyer-moore-horspool
+template <class _RandomAccessIterator1,
+          class _Hash = hash<typename iterator_traits<_RandomAccessIterator1>::value_type>,
+          class _BinaryPredicate = equal_to<>>
+class _LIBCPP_TEMPLATE_VIS boyer_moore_horspool_searcher {
+private:
+    typedef typename std::iterator_traits<_RandomAccessIterator1>::difference_type difference_type;
+    typedef typename std::iterator_traits<_RandomAccessIterator1>::value_type      value_type;
+    typedef _BMSkipTable<value_type, difference_type, _Hash, _BinaryPredicate,
+                    is_integral<value_type>::value && // what about enums?
+                    sizeof(value_type) == 1 &&
+                    is_same<_Hash, hash<value_type>>::value &&
+                    is_same<_BinaryPredicate, equal_to<>>::value
+            > skip_table_type;
+
+public:
+    boyer_moore_horspool_searcher(_RandomAccessIterator1 __f, _RandomAccessIterator1 __l,
+                _Hash __hf = _Hash(), _BinaryPredicate __pred = _BinaryPredicate())
+            : __first_(__f), __last_(__l), __pred_(__pred),
+              __pattern_length_(_VSTD::distance(__first_, __last_)),
+              __skip_{_VSTD::make_shared<skip_table_type>(__pattern_length_, __pattern_length_, __hf, __pred_)}
+        {
+    //  build the skip table
+            if ( __f != __l )
+            {
+                __l = __l - 1;
+                for ( difference_type __i = 0; __f != __l; ++__f, (void) ++__i )
+                    __skip_->insert(*__f, __pattern_length_ - 1 - __i);
+            }
+        }
+
+    template <typename _RandomAccessIterator2>
+    pair<_RandomAccessIterator2, _RandomAccessIterator2>
+    operator ()(_RandomAccessIterator2 __f, _RandomAccessIterator2 __l) const
+    {
+        static_assert(__is_same_uncvref<typename std::iterator_traits<_RandomAccessIterator1>::value_type,
+                                        typename std::iterator_traits<_RandomAccessIterator2>::value_type>::value,
+                      "Corpus and Pattern iterators must point to the same type");
+
+        if (__f      == __l )    return make_pair(__l, __l); // empty corpus
+        if (__first_ == __last_) return make_pair(__f, __f); // empty pattern
+
+    //  If the pattern is larger than the corpus, we can't find it!
+        if ( __pattern_length_ > _VSTD::distance(__f, __l))
+            return make_pair(__l, __l);
+
+    //  Do the search
+        return this->__search(__f, __l);
+    }
+
+private:
+    _RandomAccessIterator1      __first_;
+    _RandomAccessIterator1      __last_;
+    _BinaryPredicate            __pred_;
+    difference_type             __pattern_length_;
+    shared_ptr<skip_table_type> __skip_;
+
+    template <typename _RandomAccessIterator2>
+    pair<_RandomAccessIterator2, _RandomAccessIterator2>
+    __search ( _RandomAccessIterator2 __f, _RandomAccessIterator2 __l ) const {
+        _RandomAccessIterator2 __cur = __f;
+        const _RandomAccessIterator2 __last = __l - __pattern_length_;
+        const skip_table_type & __skip = *__skip_.get();
+
+        while (__cur <= __last)
+        {
+        //  Do we match right where we are?
+            difference_type __j = __pattern_length_;
+            while (__pred_(__first_[__j-1], __cur[__j-1]))
+            {
+                __j--;
+            //  We matched - we're done!
+                if ( __j == 0 )
+                    return make_pair(__cur, __cur + __pattern_length_);
+            }
+            __cur += __skip[__cur[__pattern_length_-1]];
+        }
+
+        return make_pair(__l, __l);
+    }
+};
+
+template<class _RandomAccessIterator,
+         class _Hash = hash<typename iterator_traits<_RandomAccessIterator>::value_type>,
+         class _BinaryPredicate = equal_to<>>
+_LIBCPP_INLINE_VISIBILITY
+boyer_moore_horspool_searcher<_RandomAccessIterator, _Hash, _BinaryPredicate>
+make_boyer_moore_horspool_searcher( _RandomAccessIterator __f, _RandomAccessIterator __l,
+                    _Hash __hf = _Hash(), _BinaryPredicate __p = _BinaryPredicate ())
+{
+    return boyer_moore_horspool_searcher<_RandomAccessIterator, _Hash, _BinaryPredicate>(__f, __l, __hf, __p);
+}
+
+#endif // _LIBCPP_STD_VER > 11
+
+_LIBCPP_END_NAMESPACE_LFTS
+
+_LIBCPP_POP_MACROS
+
+#endif /* _LIBCPP_EXPERIMENTAL_FUNCTIONAL */

contrib/libs/dpdk/config/arm/rte_build_config.h

@@ -0,0 +1,719 @@
+/*
+ * Autogenerated by the Meson build system.
+ * Do not edit, your changes will be lost.
+ */
+
+#pragma once
+
+#undef RTE_ARCH_32
+
+#define RTE_ARCH_64
+
+#define RTE_ARCH_ARM 1
+
+#define RTE_ARCH_ARM64 1
+
+#undef RTE_ARCH_ARM64_MEMCPY
+
+#undef RTE_ARM_USE_WFE
+
+#define RTE_BASEBAND_ACC100 1
+
+#define RTE_BASEBAND_FPGA_5GNR_FEC 1
+
+#define RTE_BASEBAND_FPGA_LTE_FEC 1
+
+#define RTE_BASEBAND_NULL 1
+
+#define RTE_BASEBAND_TURBO_SW 1
+
+#define RTE_BUS_DPAA 1
+
+#define RTE_BUS_FSLMC 1
+
+#define RTE_BUS_IFPGA 1
+
+#define RTE_BUS_PCI 1
+
+#define RTE_BUS_VDEV 1
+
+#define RTE_BUS_VMBUS 1
+
+#define RTE_CACHE_LINE_SIZE 64
+
+#define RTE_COMMON_CPT 1
+
+#define RTE_COMMON_DPAAX 1
+
+#define RTE_COMMON_IAVF 1
+
+#define RTE_COMMON_MLX5 1
+
+#define RTE_COMMON_OCTEONTX 1
+
+#define RTE_COMMON_OCTEONTX2 1
+
+#define RTE_COMMON_QAT 1
+
+#define RTE_COMMON_SFC_EFX 1
+
+#define RTE_COMPILE_TIME_CPUFLAGS RTE_CPUFLAG_NEON
+
+#define RTE_COMPRESS_OCTEONTX 1
+
+#define RTE_CRYPTO_BCMFS 1
+
+#define RTE_CRYPTO_CAAM_JR 1
+
+#define RTE_CRYPTO_DPAA2_SEC 1
+
+#define RTE_CRYPTO_DPAA_SEC 1
+
+#define RTE_CRYPTO_NITROX 1
+
+#define RTE_CRYPTO_NULL 1
+
+#define RTE_CRYPTO_OCTEONTX 1
+
+#define RTE_CRYPTO_OCTEONTX2 1
+
+#define RTE_CRYPTO_SCHEDULER 1
+
+#define RTE_CRYPTO_VIRTIO 1
+
+#define RTE_DRIVER_MEMPOOL_BUCKET_SIZE_KB 64
+
+#define RTE_EAL_NUMA_AWARE_HUGEPAGES 1
+
+#define RTE_EAL_PMD_PATH "/var/empty/dpdk-20.05-aarch64-unknown-linux-gnu/lib/dpdk/pmds-21.0"
+
+#define RTE_EAL_VFIO
+
+#undef RTE_ENABLE_TRACE_FP
+
+#define RTE_EVENT_DPAA 1
+
+#define RTE_EVENT_DPAA2 1
+
+#define RTE_EVENT_DSW 1
+
+#define RTE_EVENT_OCTEONTX 1
+
+#define RTE_EVENT_OCTEONTX2 1
+
+#define RTE_EVENT_OPDL 1
+
+#define RTE_EVENT_SKELETON 1
+
+#define RTE_EVENT_SW 1
+
+#define RTE_EXEC_ENV_LINUX 1
+
+#define RTE_FORCE_INTRINSICS 1
+
+#define RTE_HAS_LIBNUMA 1
+
+#undef RTE_LIBEAL_USE_HPET
+
+#define RTE_LIBRTE_ACL 1
+
+#define RTE_LIBRTE_AF_PACKET_PMD 1
+
+#define RTE_LIBRTE_ARK_PMD 1
+
+#define RTE_LIBRTE_ATLANTIC_PMD 1
+
+#define RTE_LIBRTE_AVP_PMD 1
+
+#define RTE_LIBRTE_AXGBE_PMD 1
+
+#define RTE_LIBRTE_BBDEV 1
+
+#define RTE_LIBRTE_BCMFS_PMD 1
+
+#define RTE_LIBRTE_BITRATESTATS 1
+
+#define RTE_LIBRTE_BNXT_PMD 1
+
+#define RTE_LIBRTE_BOND_PMD 1
+
+#define RTE_LIBRTE_BPF 1
+
+#define RTE_LIBRTE_BUCKET_MEMPOOL 1
+
+#define RTE_LIBRTE_CAAM_JR_PMD 1
+
+#define RTE_LIBRTE_CFGFILE 1
+
+#define RTE_LIBRTE_CMDLINE 1
+
+#define RTE_LIBRTE_COMPRESSDEV 1
+
+#define RTE_LIBRTE_CPT_COMMON 1
+
+#define RTE_LIBRTE_CRYPTODEV 1
+
+#define RTE_LIBRTE_CRYPTO_SCHEDULER_PMD 1
+
+#define RTE_LIBRTE_CXGBE_PMD 1
+
+#define RTE_LIBRTE_DISTRIBUTOR 1
+
+#define RTE_LIBRTE_DPAA2_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_DPAA2_MEMPOOL 1
+
+#define RTE_LIBRTE_DPAA2_PMD 1
+
+#define RTE_LIBRTE_DPAA2_SEC_PMD 1
+
+#define RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
+
+#define RTE_LIBRTE_DPAAX_COMMON 1
+
+#define RTE_LIBRTE_DPAA_BUS 1
+
+#define RTE_LIBRTE_DPAA_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_DPAA_MEMPOOL 1
+
+#define RTE_LIBRTE_DPAA_PMD 1
+
+#define RTE_LIBRTE_DPAA_SEC_PMD 1
+
+#define RTE_LIBRTE_DSW_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_E1000_PMD 1
+
+#define RTE_LIBRTE_EAL 1
+
+#define RTE_LIBRTE_EFD 1
+
+#define RTE_LIBRTE_ENA_PMD 1
+
+#define RTE_LIBRTE_ENETC_PMD 1
+
+#define RTE_LIBRTE_ENIC_PMD 1
+
+#define RTE_LIBRTE_ETHDEV 1
+
+#define RTE_LIBRTE_EVENTDEV 1
+
+#define RTE_LIBRTE_FAILSAFE_PMD 1
+
+#define RTE_LIBRTE_FIB 1
+
+#define RTE_LIBRTE_FLOW_CLASSIFY 1
+
+#define RTE_LIBRTE_FM10K_PMD 1
+
+#define RTE_LIBRTE_FSLMC_BUS 1
+
+#define RTE_LIBRTE_GRAPH 1
+
+#define RTE_LIBRTE_GRO 1
+
+#define RTE_LIBRTE_GSO 1
+
+#define RTE_LIBRTE_HASH 1
+
+#define RTE_LIBRTE_HINIC_PMD 1
+
+#define RTE_LIBRTE_HNS3_PMD 1
+
+#define RTE_LIBRTE_I40E_INC_VECTOR 1
+
+#define RTE_LIBRTE_I40E_PMD 1
+
+#define RTE_LIBRTE_IAVF_COMMON 1
+
+#define RTE_LIBRTE_IAVF_PMD 1
+
+#define RTE_LIBRTE_ICE_PMD 1
+
+#define RTE_LIBRTE_IFC_PMD 1
+
+#define RTE_LIBRTE_IFPGA_BUS 1
+
+#define RTE_LIBRTE_IGC_PMD 1
+
+#define RTE_LIBRTE_IPSEC 1
+
+#define RTE_LIBRTE_IP_FRAG 1
+
+#define RTE_LIBRTE_IXGBE_PMD 1
+
+#define RTE_LIBRTE_JOBSTATS 1
+
+#define RTE_LIBRTE_KNI 1
+
+#define RTE_LIBRTE_KNI_PMD 1
+
+#define RTE_LIBRTE_KVARGS 1
+
+#define RTE_LIBRTE_LATENCYSTATS 1
+
+#define RTE_LIBRTE_LIQUIDIO_PMD 1
+
+#define RTE_LIBRTE_LPM 1
+
+#define RTE_LIBRTE_MBUF 1
+
+#define RTE_LIBRTE_MEMBER 1
+
+#define RTE_LIBRTE_MEMIF_PMD 1
+
+#define RTE_LIBRTE_MEMPOOL 1
+
+#define RTE_LIBRTE_METER 1
+
+#define RTE_LIBRTE_METRICS 1
+
+#define RTE_LIBRTE_MLX5_COMMON 1
+
+#define RTE_LIBRTE_MLX5_PMD 1
+
+#define RTE_LIBRTE_MLX5_REGEX_PMD 1
+
+#define RTE_LIBRTE_MLX5_VDPA_PMD 1
+
+#define RTE_LIBRTE_NET 1
+
+#define RTE_LIBRTE_NETVSC_PMD 1
+
+#define RTE_LIBRTE_NFP_PMD 1
+
+#define RTE_LIBRTE_NITROX_PMD 1
+
+#define RTE_LIBRTE_NODE 1
+
+#define RTE_LIBRTE_NULL_CRYPTO_PMD 1
+
+#define RTE_LIBRTE_NULL_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX2_COMMON 1
+
+#define RTE_LIBRTE_OCTEONTX2_CRYPTO_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX2_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX2_MEMPOOL 1
+
+#define RTE_LIBRTE_OCTEONTX2_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX2_REGEX_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX_COMMON 1
+
+#define RTE_LIBRTE_OCTEONTX_COMPRESS_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX_CRYPTO_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX_MEMPOOL 1
+
+#define RTE_LIBRTE_OCTEONTX_PMD 1
+
+#define RTE_LIBRTE_OPDL_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_PCI 1
+
+#define RTE_LIBRTE_PCI_BUS 1
+
+#define RTE_LIBRTE_PDUMP 1
+
+#define RTE_LIBRTE_PFE_PMD 1
+
+#define RTE_LIBRTE_PIPELINE 1
+
+#define RTE_LIBRTE_PMD_BBDEV_ACC100 1
+
+#define RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC 1
+
+#define RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC 1
+
+#define RTE_LIBRTE_PMD_BBDEV_NULL 1
+
+#define RTE_LIBRTE_PMD_BBDEV_TURBO_SW 1
+
+#define RTE_LIBRTE_PMD_BCMFS 1
+
+#define RTE_LIBRTE_PMD_CAAM_JR 1
+
+#define RTE_LIBRTE_PMD_CRYPTO_SCHEDULER 1
+
+#define RTE_LIBRTE_PMD_DPAA2_CMDIF_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_DPAA2_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_DPAA2_SEC 1
+
+#define RTE_LIBRTE_PMD_DPAA_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_DPAA_SEC 1
+
+#define RTE_LIBRTE_PMD_DSW_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_NITROX 1
+
+#define RTE_LIBRTE_PMD_NTB_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_NULL_CRYPTO 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX_COMPRESS 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX_CRYPTO 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_OPDL_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_SKELETON_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_SKELETON_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_SW_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_VIRTIO_CRYPTO 1
+
+#define RTE_LIBRTE_PORT 1
+
+#define RTE_LIBRTE_POWER 1
+
+#define RTE_LIBRTE_QAT_COMMON 1
+
+#define RTE_LIBRTE_QEDE_PMD 1
+
+#define RTE_LIBRTE_RAWDEV 1
+
+#define RTE_LIBRTE_RCU 1
+
+#define RTE_LIBRTE_REGEXDEV 1
+
+#define RTE_LIBRTE_REORDER 1
+
+#define RTE_LIBRTE_RIB 1
+
+#define RTE_LIBRTE_RING 1
+
+#define RTE_LIBRTE_RING_MEMPOOL 1
+
+#define RTE_LIBRTE_RING_PMD 1
+
+#define RTE_LIBRTE_SCHED 1
+
+#define RTE_LIBRTE_SECURITY 1
+
+#define RTE_LIBRTE_SFC_EFX_COMMON 1
+
+#define RTE_LIBRTE_SFC_PMD 1
+
+#define RTE_LIBRTE_SKELETON_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_SOFTNIC_PMD 1
+
+#define RTE_LIBRTE_STACK 1
+
+#define RTE_LIBRTE_STACK_MEMPOOL 1
+
+#define RTE_LIBRTE_SW_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_TABLE 1
+
+#define RTE_LIBRTE_TAP_PMD 1
+
+#define RTE_LIBRTE_TELEMETRY 1
+
+#define RTE_LIBRTE_THUNDERX_PMD 1
+
+#define RTE_LIBRTE_TIMER 1
+
+#define RTE_LIBRTE_TXGBE_PMD 1
+
+#define RTE_LIBRTE_VDEV_BUS 1
+
+#define RTE_LIBRTE_VDEV_NETVSC_PMD 1
+
+#define RTE_LIBRTE_VHOST 1
+
+#define RTE_LIBRTE_VHOST_NUMA 1
+
+#define RTE_LIBRTE_VHOST_PMD 1
+
+#define RTE_LIBRTE_VHOST_POSTCOPY
+
+#define RTE_LIBRTE_VIRTIO_CRYPTO_PMD 1
+
+#define RTE_LIBRTE_VIRTIO_PMD 1
+
+#define RTE_LIBRTE_VMBUS_BUS 1
+
+#define RTE_LIBRTE_VMXNET3_PMD 1
+
+#define RTE_LIB_ACL 1
+
+#define RTE_LIB_BBDEV 1
+
+#define RTE_LIB_BITRATESTATS 1
+
+#define RTE_LIB_BPF 1
+
+#define RTE_LIB_CFGFILE 1
+
+#define RTE_LIB_CMDLINE 1
+
+#define RTE_LIB_COMPRESSDEV 1
+
+#define RTE_LIB_CRYPTODEV 1
+
+#define RTE_LIB_DISTRIBUTOR 1
+
+#define RTE_LIB_EAL 1
+
+#define RTE_LIB_EFD 1
+
+#define RTE_LIB_ETHDEV 1
+
+#define RTE_LIB_EVENTDEV 1
+
+#define RTE_LIB_FIB 1
+
+#define RTE_LIB_FLOW_CLASSIFY 1
+
+#define RTE_LIB_GRAPH 1
+
+#define RTE_LIB_GRO 1
+
+#define RTE_LIB_GSO 1
+
+#define RTE_LIB_HASH 1
+
+#define RTE_LIB_IPSEC 1
+
+#define RTE_LIB_IP_FRAG 1
+
+#define RTE_LIB_JOBSTATS 1
+
+#define RTE_LIB_KNI 1
+
+#define RTE_LIB_KVARGS 1
+
+#define RTE_LIB_LATENCYSTATS 1
+
+#define RTE_LIB_LPM 1
+
+#define RTE_LIB_MBUF 1
+
+#define RTE_LIB_MEMBER 1
+
+#define RTE_LIB_MEMPOOL 1
+
+#define RTE_LIB_METER 1
+
+#define RTE_LIB_METRICS 1
+
+#define RTE_LIB_NET 1
+
+#define RTE_LIB_NODE 1
+
+#define RTE_LIB_PCI 1
+
+#define RTE_LIB_PDUMP 1
+
+#define RTE_LIB_PIPELINE 1
+
+#define RTE_LIB_PORT 1
+
+#define RTE_LIB_POWER 1
+
+#define RTE_LIB_RAWDEV 1
+
+#define RTE_LIB_RCU 1
+
+#define RTE_LIB_REGEXDEV 1
+
+#define RTE_LIB_REORDER 1
+
+#define RTE_LIB_RIB 1
+
+#define RTE_LIB_RING 1
+
+#define RTE_LIB_SCHED 1
+
+#define RTE_LIB_SECURITY 1
+
+#define RTE_LIB_STACK 1
+
+#define RTE_LIB_TABLE 1
+
+#define RTE_LIB_TELEMETRY 1
+
+#define RTE_LIB_TIMER 1
+
+#define RTE_LIB_VHOST 1
+
+#define RTE_MACHINE "armv8a"
+
+#define RTE_MAX_ETHPORTS 32
+
+#define RTE_MAX_LCORE 256
+
+#define RTE_MAX_MEM_MB 524288
+
+#define RTE_MAX_NUMA_NODES 4
+
+#define RTE_MAX_VFIO_GROUPS 64
+
+#define RTE_MEMPOOL_BUCKET 1
+
+#define RTE_MEMPOOL_DPAA 1
+
+#define RTE_MEMPOOL_DPAA2 1
+
+#define RTE_MEMPOOL_OCTEONTX 1
+
+#define RTE_MEMPOOL_OCTEONTX2 1
+
+#define RTE_MEMPOOL_RING 1
+
+#define RTE_MEMPOOL_STACK 1
+
+#define RTE_NET_AF_PACKET 1
+
+#define RTE_NET_ARK 1
+
+#define RTE_NET_ATLANTIC 1
+
+#define RTE_NET_AVP 1
+
+#define RTE_NET_AXGBE 1
+
+#define RTE_NET_BNXT 1
+
+#define RTE_NET_BOND 1
+
+#define RTE_NET_CXGBE 1
+
+#define RTE_NET_DPAA 1
+
+#define RTE_NET_DPAA2 1
+
+#define RTE_NET_E1000 1
+
+#define RTE_NET_ENA 1
+
+#define RTE_NET_ENETC 1
+
+#define RTE_NET_ENIC 1
+
+#define RTE_NET_FAILSAFE 1
+
+#define RTE_NET_FM10K 1
+
+#define RTE_NET_HINIC 1
+
+#define RTE_NET_HNS3 1
+
+#define RTE_NET_I40E 1
+
+#define RTE_NET_IAVF 1
+
+#define RTE_NET_ICE 1
+
+#define RTE_NET_IGC 1
+
+#define RTE_NET_IXGBE 1
+
+#define RTE_NET_KNI 1
+
+#define RTE_NET_LIQUIDIO 1
+
+#define RTE_NET_MEMIF 1
+
+#define RTE_NET_MLX5 1
+
+#define RTE_NET_NETVSC 1
+
+#define RTE_NET_NFP 1
+
+#define RTE_NET_NULL 1
+
+#define RTE_NET_OCTEONTX 1
+
+#define RTE_NET_OCTEONTX2 1
+
+#define RTE_NET_PFE 1
+
+#define RTE_NET_QEDE 1
+
+#define RTE_NET_RING 1
+
+#define RTE_NET_SFC 1
+
+#define RTE_NET_SOFTNIC 1
+
+#define RTE_NET_TAP 1
+
+#define RTE_NET_THUNDERX 1
+
+#define RTE_NET_TXGBE 1
+
+#define RTE_NET_VDEV_NETVSC 1
+
+#define RTE_NET_VHOST 1
+
+#define RTE_NET_VIRTIO 1
+
+#define RTE_NET_VMXNET3 1
+
+#define RTE_RAW_DPAA2_CMDIF 1
+
+#define RTE_RAW_DPAA2_QDMA 1
+
+#define RTE_RAW_NTB 1
+
+#define RTE_RAW_OCTEONTX2_DMA 1
+
+#define RTE_RAW_OCTEONTX2_EP 1
+
+#define RTE_RAW_SKELETON 1
+
+#define RTE_REGEX_MLX5 1
+
+#define RTE_REGEX_OCTEONTX2 1
+
+#undef RTE_SCHED_VECTOR
+
+#define RTE_TOOLCHAIN "gcc"
+
+#define RTE_TOOLCHAIN_GCC 1
+
+#define RTE_USE_C11_MEM_MODEL
+
+#define RTE_VDPA_IFC 1
+
+#define RTE_VDPA_MLX5 1
+
+#define RTE_VER_MINOR 0
+
+#define RTE_VER_MONTH 11
+
+#define RTE_VER_RELEASE 99
+
+#define RTE_VER_SUFFIX ""
+
+#define RTE_VER_YEAR 20
+
+#define RTE_VIRTIO_USER 1
+

contrib/libs/dpdk/config/rte_build_config.h

@@ -0,0 +1,6 @@
+
+#if defined(__aarch64__)
+#   include <arm/rte_build_config.h>
+#elif defined(__x86_64__)
+#   include <x86/rte_build_config.h>
+#endif

contrib/libs/dpdk/config/rte_compatibility_defines.h

@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Intel Corporation
+ */
+
+#ifndef _RTE_CONFIG_H_
+#error "This file should only be included via rte_config.h"
+#endif
+
+/*
+ * NOTE: these defines are for compatibility only and will be removed in a
+ * future DPDK release.
+ */
+
+#ifdef RTE_LIBRTE_BITRATESTATS
+#define RTE_LIBRTE_BITRATE
+#endif
+
+#ifdef RTE_LIBRTE_LATENCYSTATS
+#define RTE_LIBRTE_LATENCY_STATS
+#endif
+
+#ifdef RTE_LIBRTE_DPAAX_COMMON
+#define RTE_LIBRTE_COMMON_DPAAX
+#endif
+
+#ifdef RTE_LIBRTE_VMBUS_BUS
+#define RTE_LIBRTE_VMBUS
+#endif
+
+#ifdef RTE_LIBRTE_BUCKET_MEMPOOL
+#define RTE_DRIVER_MEMPOOL_BUCKET
+#endif
+
+#ifdef RTE_LIBRTE_RING_MEMPOOL
+#define RTE_DRIVER_MEMPOOL_RING
+#endif
+
+#ifdef RTE_LIBRTE_STACK_MEMPOOL
+#define RTE_DRIVER_MEMPOOL_STACK
+#endif
+
+#ifdef RTE_LIBRTE_AF_PACKET_PMD
+#define RTE_LIBRTE_PMD_AF_PACKET
+#endif
+
+#ifdef RTE_LIBRTE_AF_XDP_PMD
+#define RTE_LIBRTE_PMD_AF_XDP
+#endif
+
+#ifdef RTE_LIBRTE_BOND_PMD
+#define RTE_LIBRTE_PMD_BOND
+#endif
+
+#ifdef RTE_LIBRTE_E1000_PMD
+#define RTE_LIBRTE_EM_PMD
+#endif
+
+#ifdef RTE_LIBRTE_E1000_PMD
+#define RTE_LIBRTE_IGB_PMD
+#endif
+
+#ifdef RTE_LIBRTE_FAILSAFE_PMD
+#define RTE_LIBRTE_PMD_FAILSAFE
+#endif
+
+#ifdef RTE_LIBRTE_KNI_PMD
+#define RTE_LIBRTE_PMD_KNI
+#endif
+
+#ifdef RTE_LIBRTE_LIQUIDIO_PMD
+#define RTE_LIBRTE_LIO_PMD
+#endif
+
+#ifdef RTE_LIBRTE_MEMIF_PMD
+#define RTE_LIBRTE_PMD_MEMIF
+#endif
+
+#ifdef RTE_LIBRTE_NULL_PMD
+#define RTE_LIBRTE_PMD_NULL
+#endif
+
+#ifdef RTE_LIBRTE_PCAP_PMD
+#define RTE_LIBRTE_PMD_PCAP
+#endif
+
+#ifdef RTE_LIBRTE_RING_PMD
+#define RTE_LIBRTE_PMD_RING
+#endif
+
+#ifdef RTE_LIBRTE_SFC_PMD
+#define RTE_LIBRTE_SFC_EFX_PMD
+#endif
+
+#ifdef RTE_LIBRTE_SOFTNIC_PMD
+#define RTE_LIBRTE_PMD_SOFTNIC
+#endif
+
+#ifdef RTE_LIBRTE_SZEDATA2_PMD
+#define RTE_LIBRTE_PMD_SZEDATA2
+#endif
+
+#ifdef RTE_LIBRTE_TAP_PMD
+#define RTE_LIBRTE_PMD_TAP
+#endif
+
+#ifdef RTE_LIBRTE_THUNDERX_PMD
+#define RTE_LIBRTE_THUNDERX_NICVF_PMD
+#endif
+
+#ifdef RTE_LIBRTE_VHOST_PMD
+#define RTE_LIBRTE_PMD_VHOST
+#endif
+
+#ifdef RTE_LIBRTE_PMD_ARMV8
+#define RTE_LIBRTE_PMD_ARMV8_CRYPTO
+#endif
+
+#ifdef RTE_LIBRTE_PMD_MVSAM
+#define RTE_LIBRTE_PMD_MVSAM_CRYPTO
+#endif
+
+#ifdef RTE_LIBRTE_PMD_OCTEONTX_COMPRESS
+#define RTE_LIBRTE_PMD_OCTEONTX_ZIPVF
+#endif
+
+#ifdef RTE_LIBRTE_PMD_OCTEONTX_EVENTDEV
+#define RTE_LIBRTE_PMD_OCTEONTX_SSOVF
+#endif
+

contrib/libs/dpdk/config/rte_config.h

@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Intel Corporation
+ */
+
+/**
+ * @file Header file containing DPDK compilation parameters
+ *
+ * Header file containing DPDK compilation parameters. Also include the
+ * meson-generated header file containing the detected parameters that
+ * are variable across builds or build environments.
+ */
+#ifndef _RTE_CONFIG_H_
+#define _RTE_CONFIG_H_
+
+#include <rte_build_config.h>
+#include "rte_compatibility_defines.h"
+
+/* legacy defines */
+#ifdef RTE_EXEC_ENV_LINUX
+#define RTE_EXEC_ENV_LINUXAPP 1
+#endif
+#ifdef RTE_EXEC_ENV_FREEBSD
+#define RTE_EXEC_ENV_BSDAPP 1
+#endif
+
+/* String that appears before the version number */
+#define RTE_VER_PREFIX "DPDK"
+
+/****** library defines ********/
+
+/* EAL defines */
+#define RTE_MAX_HEAPS 32
+#define RTE_MAX_MEMSEG_LISTS 128
+#define RTE_MAX_MEMSEG_PER_LIST 8192
+#define RTE_MAX_MEM_MB_PER_LIST 32768
+#define RTE_MAX_MEMSEG_PER_TYPE 32768
+#define RTE_MAX_MEM_MB_PER_TYPE 65536
+#define RTE_MAX_MEMZONE 2560
+#define RTE_MAX_TAILQ 32
+#define RTE_LOG_DP_LEVEL RTE_LOG_INFO
+#define RTE_BACKTRACE 1
+#define RTE_MAX_VFIO_CONTAINERS 64
+
+/* bsd module defines */
+#define RTE_CONTIGMEM_MAX_NUM_BUFS 64
+#define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1
+#define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024)
+
+/* mempool defines */
+#define RTE_MEMPOOL_CACHE_MAX_SIZE 512
+
+/* mbuf defines */
+#define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc"
+#define RTE_MBUF_REFCNT_ATOMIC 1
+#define RTE_PKTMBUF_HEADROOM 128
+
+/* ether defines */
+#define RTE_MAX_QUEUES_PER_PORT 1024
+#define RTE_ETHDEV_QUEUE_STAT_CNTRS 16 /* max 256 */
+#define RTE_ETHDEV_RXTX_CALLBACKS 1
+
+/* cryptodev defines */
+#define RTE_CRYPTO_MAX_DEVS 64
+#define RTE_CRYPTODEV_NAME_LEN 64
+
+/* compressdev defines */
+#define RTE_COMPRESS_MAX_DEVS 64
+
+/* regexdev defines */
+#define RTE_MAX_REGEXDEV_DEVS 32
+
+/* eventdev defines */
+#define RTE_EVENT_MAX_DEVS 16
+#define RTE_EVENT_MAX_QUEUES_PER_DEV 255
+#define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32
+#define RTE_EVENT_ETH_INTR_RING_SIZE 1024
+#define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32
+#define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32
+
+/* rawdev defines */
+#define RTE_RAWDEV_MAX_DEVS 64
+
+/* ip_fragmentation defines */
+#define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4
+#undef RTE_LIBRTE_IP_FRAG_TBL_STAT
+
+/* rte_power defines */
+#define RTE_MAX_LCORE_FREQS 64
+
+/* rte_sched defines */
+#undef RTE_SCHED_RED
+#undef RTE_SCHED_COLLECT_STATS
+#undef RTE_SCHED_SUBPORT_TC_OV
+#define RTE_SCHED_PORT_N_GRINDERS 8
+#undef RTE_SCHED_VECTOR
+
+/* KNI defines */
+#define RTE_KNI_PREEMPT_DEFAULT 1
+
+/* rte_graph defines */
+#define RTE_GRAPH_BURST_SIZE 256
+#define RTE_LIBRTE_GRAPH_STATS 1
+
+/****** driver defines ********/
+
+/* Packet prefetching in PMDs */
+#define RTE_PMD_PACKET_PREFETCH 1
+
+/* QuickAssist device */
+/* Max. number of QuickAssist devices which can be attached */
+#define RTE_PMD_QAT_MAX_PCI_DEVICES 48
+#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
+#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
+
+/* virtio crypto defines */
+#define RTE_MAX_VIRTIO_CRYPTO 32
+
+/* DPAA SEC max cryptodev devices*/
+#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV	4
+
+/* fm10k defines */
+#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1
+
+/* hns3 defines */
+#define RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 256
+
+/* i40e defines */
+#define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1
+#undef RTE_LIBRTE_I40E_16BYTE_RX_DESC
+#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64
+#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
+#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4
+
+/* Ring net PMD settings */
+#define RTE_PMD_RING_MAX_RX_RINGS 16
+#define RTE_PMD_RING_MAX_TX_RINGS 16
+
+/* QEDE PMD defines */
+#define RTE_LIBRTE_QEDE_FW ""
+
+/* DLB PMD defines */
+#define RTE_LIBRTE_PMD_DLB_POLL_INTERVAL 1000
+#define RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE  0
+#undef RTE_LIBRTE_PMD_DLB_QUELL_STATS
+#define RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA 32
+
+/* DLB2 defines */
+#define RTE_LIBRTE_PMD_DLB2_POLL_INTERVAL 1000
+#define RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE  0
+#undef RTE_LIBRTE_PMD_DLB2_QUELL_STATS
+#define RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA 32
+#define RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH 256
+
+#endif /* _RTE_CONFIG_H_ */

contrib/libs/dpdk/config/x86/rte_build_config.h

@@ -0,0 +1,729 @@
+/*
+ * Autogenerated by the Meson build system.
+ * Do not edit, your changes will be lost.
+ */
+
+#pragma once
+
+#define RTE_ARCH x86_64
+
+#undef RTE_ARCH_32
+
+#define RTE_ARCH_64
+
+#define RTE_ARCH_X86 1
+
+#define RTE_ARCH_X86_64 1
+
+#define RTE_BASEBAND_ACC100 1
+
+#define RTE_BASEBAND_FPGA_5GNR_FEC 1
+
+#define RTE_BASEBAND_FPGA_LTE_FEC 1
+
+#define RTE_BASEBAND_NULL 1
+
+#define RTE_BASEBAND_TURBO_SW 1
+
+#define RTE_BUS_DPAA 1
+
+#define RTE_BUS_FSLMC 1
+
+#define RTE_BUS_IFPGA 1
+
+#define RTE_BUS_PCI 1
+
+#define RTE_BUS_VDEV 1
+
+#define RTE_BUS_VMBUS 1
+
+#define RTE_CACHE_LINE_SIZE 64
+
+#define RTE_COMMON_CPT 1
+
+#define RTE_COMMON_DPAAX 1
+
+#define RTE_COMMON_IAVF 1
+
+#define RTE_COMMON_MLX5 1
+
+#define RTE_COMMON_OCTEONTX 1
+
+#define RTE_COMMON_OCTEONTX2 1
+
+#define RTE_COMMON_QAT 1
+
+#define RTE_COMMON_SFC_EFX 1
+
+#define RTE_COMPILE_TIME_CPUFLAGS RTE_CPUFLAG_SSE,RTE_CPUFLAG_SSE2,RTE_CPUFLAG_SSE3,RTE_CPUFLAG_SSSE3,RTE_CPUFLAG_SSE4_1,RTE_CPUFLAG_SSE4_2
+
+#define RTE_COMPRESS_OCTEONTX 1
+
+#define RTE_CRYPTO_BCMFS 1
+
+#define RTE_CRYPTO_CAAM_JR 1
+
+#define RTE_CRYPTO_DPAA2_SEC 1
+
+#define RTE_CRYPTO_DPAA_SEC 1
+
+#define RTE_CRYPTO_NITROX 1
+
+#define RTE_CRYPTO_NULL 1
+
+#define RTE_CRYPTO_OCTEONTX 1
+
+#define RTE_CRYPTO_OCTEONTX2 1
+
+#define RTE_CRYPTO_SCHEDULER 1
+
+#define RTE_CRYPTO_VIRTIO 1
+
+#define RTE_DRIVER_MEMPOOL_BUCKET_SIZE_KB 64
+
+#define RTE_EAL_NUMA_AWARE_HUGEPAGES 1
+
+#define RTE_EAL_PMD_PATH "/var/empty/dpdk-20.05/lib/dpdk/pmds-21.0"
+
+#define RTE_EAL_VFIO
+
+#undef RTE_ENABLE_TRACE_FP
+
+#define RTE_EVENT_DLB 1
+
+#define RTE_EVENT_DLB2 1
+
+#define RTE_EVENT_DPAA 1
+
+#define RTE_EVENT_DPAA2 1
+
+#define RTE_EVENT_DSW 1
+
+#define RTE_EVENT_OCTEONTX 1
+
+#define RTE_EVENT_OCTEONTX2 1
+
+#define RTE_EVENT_OPDL 1
+
+#define RTE_EVENT_SKELETON 1
+
+#define RTE_EVENT_SW 1
+
+#define RTE_EXEC_ENV_LINUX 1
+
+#define RTE_HAS_LIBNUMA 1
+
+#undef RTE_LIBEAL_USE_HPET
+
+#define RTE_LIBRTE_ACL 1
+
+#define RTE_LIBRTE_AF_PACKET_PMD 1
+
+#define RTE_LIBRTE_ARK_PMD 1
+
+#define RTE_LIBRTE_ATLANTIC_PMD 1
+
+#define RTE_LIBRTE_AVP_PMD 1
+
+#define RTE_LIBRTE_AXGBE_PMD 1
+
+#define RTE_LIBRTE_BBDEV 1
+
+#define RTE_LIBRTE_BCMFS_PMD 1
+
+#define RTE_LIBRTE_BITRATESTATS 1
+
+#define RTE_LIBRTE_BNXT_PMD 1
+
+#define RTE_LIBRTE_BOND_PMD 1
+
+#define RTE_LIBRTE_BPF 1
+
+#define RTE_LIBRTE_BUCKET_MEMPOOL 1
+
+#define RTE_LIBRTE_CAAM_JR_PMD 1
+
+#define RTE_LIBRTE_CFGFILE 1
+
+#define RTE_LIBRTE_CMDLINE 1
+
+#define RTE_LIBRTE_COMPRESSDEV 1
+
+#define RTE_LIBRTE_CPT_COMMON 1
+
+#define RTE_LIBRTE_CRYPTODEV 1
+
+#define RTE_LIBRTE_CRYPTO_SCHEDULER_PMD 1
+
+#define RTE_LIBRTE_CXGBE_PMD 1
+
+#define RTE_LIBRTE_DISTRIBUTOR 1
+
+#define RTE_LIBRTE_DLB2_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_DLB_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_DPAA2_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_DPAA2_MEMPOOL 1
+
+#define RTE_LIBRTE_DPAA2_PMD 1
+
+#define RTE_LIBRTE_DPAA2_SEC_PMD 1
+
+#define RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
+
+#define RTE_LIBRTE_DPAAX_COMMON 1
+
+#define RTE_LIBRTE_DPAA_BUS 1
+
+#define RTE_LIBRTE_DPAA_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_DPAA_MEMPOOL 1
+
+#define RTE_LIBRTE_DPAA_PMD 1
+
+#define RTE_LIBRTE_DPAA_SEC_PMD 1
+
+#define RTE_LIBRTE_DSW_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_E1000_PMD 1
+
+#define RTE_LIBRTE_EAL 1
+
+#define RTE_LIBRTE_EFD 1
+
+#define RTE_LIBRTE_ENA_PMD 1
+
+#define RTE_LIBRTE_ENETC_PMD 1
+
+#define RTE_LIBRTE_ENIC_PMD 1
+
+#define RTE_LIBRTE_ETHDEV 1
+
+#define RTE_LIBRTE_EVENTDEV 1
+
+#define RTE_LIBRTE_FAILSAFE_PMD 1
+
+#define RTE_LIBRTE_FIB 1
+
+#define RTE_LIBRTE_FLOW_CLASSIFY 1
+
+#define RTE_LIBRTE_FM10K_INC_VECTOR 1
+
+#define RTE_LIBRTE_FM10K_PMD 1
+
+#define RTE_LIBRTE_FSLMC_BUS 1
+
+#define RTE_LIBRTE_GRAPH 1
+
+#define RTE_LIBRTE_GRO 1
+
+#define RTE_LIBRTE_GSO 1
+
+#define RTE_LIBRTE_HASH 1
+
+#define RTE_LIBRTE_HINIC_PMD 1
+
+#define RTE_LIBRTE_HNS3_PMD 1
+
+#define RTE_LIBRTE_I40E_INC_VECTOR 1
+
+#define RTE_LIBRTE_I40E_PMD 1
+
+#define RTE_LIBRTE_IAVF_COMMON 1
+
+#define RTE_LIBRTE_IAVF_PMD 1
+
+#define RTE_LIBRTE_ICE_PMD 1
+
+#define RTE_LIBRTE_IFC_PMD 1
+
+#define RTE_LIBRTE_IFPGA_BUS 1
+
+#define RTE_LIBRTE_IGC_PMD 1
+
+#define RTE_LIBRTE_IPSEC 1
+
+#define RTE_LIBRTE_IP_FRAG 1
+
+#define RTE_LIBRTE_IXGBE_PMD 1
+
+#define RTE_LIBRTE_JOBSTATS 1
+
+#define RTE_LIBRTE_KNI 1
+
+#define RTE_LIBRTE_KNI_PMD 1
+
+#define RTE_LIBRTE_KVARGS 1
+
+#define RTE_LIBRTE_LATENCYSTATS 1
+
+#define RTE_LIBRTE_LIQUIDIO_PMD 1
+
+#define RTE_LIBRTE_LPM 1
+
+#define RTE_LIBRTE_MBUF 1
+
+#define RTE_LIBRTE_MEMBER 1
+
+#define RTE_LIBRTE_MEMIF_PMD 1
+
+#define RTE_LIBRTE_MEMPOOL 1
+
+#define RTE_LIBRTE_METER 1
+
+#define RTE_LIBRTE_METRICS 1
+
+#define RTE_LIBRTE_MLX5_COMMON 1
+
+#define RTE_LIBRTE_MLX5_PMD 1
+
+#define RTE_LIBRTE_MLX5_REGEX_PMD 1
+
+#define RTE_LIBRTE_MLX5_VDPA_PMD 1
+
+#define RTE_LIBRTE_NET 1
+
+#define RTE_LIBRTE_NETVSC_PMD 1
+
+#define RTE_LIBRTE_NFP_PMD 1
+
+#define RTE_LIBRTE_NITROX_PMD 1
+
+#define RTE_LIBRTE_NODE 1
+
+#define RTE_LIBRTE_NULL_CRYPTO_PMD 1
+
+#define RTE_LIBRTE_NULL_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX2_COMMON 1
+
+#define RTE_LIBRTE_OCTEONTX2_CRYPTO_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX2_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX2_MEMPOOL 1
+
+#define RTE_LIBRTE_OCTEONTX2_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX2_REGEX_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX_COMMON 1
+
+#define RTE_LIBRTE_OCTEONTX_COMPRESS_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX_CRYPTO_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_OCTEONTX_MEMPOOL 1
+
+#define RTE_LIBRTE_OCTEONTX_PMD 1
+
+#define RTE_LIBRTE_OPDL_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_PCI 1
+
+#define RTE_LIBRTE_PCI_BUS 1
+
+#define RTE_LIBRTE_PDUMP 1
+
+#define RTE_LIBRTE_PFE_PMD 1
+
+#define RTE_LIBRTE_PIPELINE 1
+
+#define RTE_LIBRTE_PMD_BBDEV_ACC100 1
+
+#define RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC 1
+
+#define RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC 1
+
+#define RTE_LIBRTE_PMD_BBDEV_NULL 1
+
+#define RTE_LIBRTE_PMD_BBDEV_TURBO_SW 1
+
+#define RTE_LIBRTE_PMD_BCMFS 1
+
+#define RTE_LIBRTE_PMD_CAAM_JR 1
+
+#define RTE_LIBRTE_PMD_CRYPTO_SCHEDULER 1
+
+#define RTE_LIBRTE_PMD_DLB2_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_DLB_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_DPAA2_CMDIF_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_DPAA2_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_DPAA2_SEC 1
+
+#define RTE_LIBRTE_PMD_DPAA_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_DPAA_SEC 1
+
+#define RTE_LIBRTE_PMD_DSW_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_IOAT_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_NITROX 1
+
+#define RTE_LIBRTE_PMD_NTB_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_NULL_CRYPTO 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX_COMPRESS 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX_CRYPTO 1
+
+#define RTE_LIBRTE_PMD_OCTEONTX_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_OPDL_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_SKELETON_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_SKELETON_RAWDEV 1
+
+#define RTE_LIBRTE_PMD_SW_EVENTDEV 1
+
+#define RTE_LIBRTE_PMD_VIRTIO_CRYPTO 1
+
+#define RTE_LIBRTE_PORT 1
+
+#define RTE_LIBRTE_POWER 1
+
+#define RTE_LIBRTE_QAT_COMMON 1
+
+#define RTE_LIBRTE_QEDE_PMD 1
+
+#define RTE_LIBRTE_RAWDEV 1
+
+#define RTE_LIBRTE_RCU 1
+
+#define RTE_LIBRTE_REGEXDEV 1
+
+#define RTE_LIBRTE_REORDER 1
+
+#define RTE_LIBRTE_RIB 1
+
+#define RTE_LIBRTE_RING 1
+
+#define RTE_LIBRTE_RING_MEMPOOL 1
+
+#define RTE_LIBRTE_RING_PMD 1
+
+#define RTE_LIBRTE_SCHED 1
+
+#define RTE_LIBRTE_SECURITY 1
+
+#define RTE_LIBRTE_SFC_EFX_COMMON 1
+
+#define RTE_LIBRTE_SFC_PMD 1
+
+#define RTE_LIBRTE_SKELETON_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_SOFTNIC_PMD 1
+
+#define RTE_LIBRTE_STACK 1
+
+#define RTE_LIBRTE_STACK_MEMPOOL 1
+
+#define RTE_LIBRTE_SW_EVENTDEV_PMD 1
+
+#define RTE_LIBRTE_TABLE 1
+
+#define RTE_LIBRTE_TAP_PMD 1
+
+#define RTE_LIBRTE_TELEMETRY 1
+
+#define RTE_LIBRTE_THUNDERX_PMD 1
+
+#define RTE_LIBRTE_TIMER 1
+
+#define RTE_LIBRTE_TXGBE_PMD 1
+
+#define RTE_LIBRTE_VDEV_BUS 1
+
+#define RTE_LIBRTE_VDEV_NETVSC_PMD 1
+
+#define RTE_LIBRTE_VHOST 1
+
+#define RTE_LIBRTE_VHOST_NUMA 1
+
+#define RTE_LIBRTE_VHOST_PMD 1
+
+#define RTE_LIBRTE_VHOST_POSTCOPY
+
+#define RTE_LIBRTE_VIRTIO_CRYPTO_PMD 1
+
+#define RTE_LIBRTE_VIRTIO_PMD 1
+
+#define RTE_LIBRTE_VMBUS_BUS 1
+
+#define RTE_LIBRTE_VMXNET3_PMD 1
+
+#define RTE_LIB_ACL 1
+
+#define RTE_LIB_BBDEV 1
+
+#define RTE_LIB_BITRATESTATS 1
+
+#define RTE_LIB_BPF 1
+
+#define RTE_LIB_CFGFILE 1
+
+#define RTE_LIB_CMDLINE 1
+
+#define RTE_LIB_COMPRESSDEV 1
+
+#define RTE_LIB_CRYPTODEV 1
+
+#define RTE_LIB_DISTRIBUTOR 1
+
+#define RTE_LIB_EAL 1
+
+#define RTE_LIB_EFD 1
+
+#define RTE_LIB_ETHDEV 1
+
+#define RTE_LIB_EVENTDEV 1
+
+#define RTE_LIB_FIB 1
+
+#define RTE_LIB_FLOW_CLASSIFY 1
+
+#define RTE_LIB_GRAPH 1
+
+#define RTE_LIB_GRO 1
+
+#define RTE_LIB_GSO 1
+
+#define RTE_LIB_HASH 1
+
+#define RTE_LIB_IPSEC 1
+
+#define RTE_LIB_IP_FRAG 1
+
+#define RTE_LIB_JOBSTATS 1
+
+#define RTE_LIB_KNI 1
+
+#define RTE_LIB_KVARGS 1
+
+#define RTE_LIB_LATENCYSTATS 1
+
+#define RTE_LIB_LPM 1
+
+#define RTE_LIB_MBUF 1
+
+#define RTE_LIB_MEMBER 1
+
+#define RTE_LIB_MEMPOOL 1
+
+#define RTE_LIB_METER 1
+
+#define RTE_LIB_METRICS 1
+
+#define RTE_LIB_NET 1
+
+#define RTE_LIB_NODE 1
+
+#define RTE_LIB_PCI 1
+
+#define RTE_LIB_PDUMP 1
+
+#define RTE_LIB_PIPELINE 1
+
+#define RTE_LIB_PORT 1
+
+#define RTE_LIB_POWER 1
+
+#define RTE_LIB_RAWDEV 1
+
+#define RTE_LIB_RCU 1
+
+#define RTE_LIB_REGEXDEV 1
+
+#define RTE_LIB_REORDER 1
+
+#define RTE_LIB_RIB 1
+
+#define RTE_LIB_RING 1
+
+#define RTE_LIB_SCHED 1
+
+#define RTE_LIB_SECURITY 1
+
+#define RTE_LIB_STACK 1
+
+#define RTE_LIB_TABLE 1
+
+#define RTE_LIB_TELEMETRY 1
+
+#define RTE_LIB_TIMER 1
+
+#define RTE_LIB_VHOST 1
+
+#define RTE_MACHINE native
+
+#define RTE_MAX_ETHPORTS 32
+
+#define RTE_MAX_LCORE 256
+
+#define RTE_MAX_MEM_MB 524288
+
+#define RTE_MAX_NUMA_NODES 4
+
+#define RTE_MAX_VFIO_GROUPS 64
+
+#define RTE_MEMPOOL_BUCKET 1
+
+#define RTE_MEMPOOL_DPAA 1
+
+#define RTE_MEMPOOL_DPAA2 1
+
+#define RTE_MEMPOOL_OCTEONTX 1
+
+#define RTE_MEMPOOL_OCTEONTX2 1
+
+#define RTE_MEMPOOL_RING 1
+
+#define RTE_MEMPOOL_STACK 1
+
+#define RTE_NET_AF_PACKET 1
+
+#define RTE_NET_ARK 1
+
+#define RTE_NET_ATLANTIC 1
+
+#define RTE_NET_AVP 1
+
+#define RTE_NET_AXGBE 1
+
+#define RTE_NET_BNXT 1
+
+#define RTE_NET_BOND 1
+
+#define RTE_NET_CXGBE 1
+
+#define RTE_NET_DPAA 1
+
+#define RTE_NET_DPAA2 1
+
+#define RTE_NET_E1000 1
+
+#define RTE_NET_ENA 1
+
+#define RTE_NET_ENETC 1
+
+#define RTE_NET_ENIC 1
+
+#define RTE_NET_FAILSAFE 1
+
+#define RTE_NET_FM10K 1
+
+#define RTE_NET_HINIC 1
+
+#define RTE_NET_HNS3 1
+
+#define RTE_NET_I40E 1
+
+#define RTE_NET_IAVF 1
+
+#define RTE_NET_ICE 1
+
+#define RTE_NET_IGC 1
+
+#define RTE_NET_IXGBE 1
+
+#define RTE_NET_KNI 1
+
+#define RTE_NET_LIQUIDIO 1
+
+#define RTE_NET_MEMIF 1
+
+#define RTE_NET_MLX5 1
+
+#define RTE_NET_NETVSC 1
+
+#define RTE_NET_NFP 1
+
+#define RTE_NET_NULL 1
+
+#define RTE_NET_OCTEONTX 1
+
+#define RTE_NET_OCTEONTX2 1
+
+#define RTE_NET_PFE 1
+
+#define RTE_NET_QEDE 1
+
+#define RTE_NET_RING 1
+
+#define RTE_NET_SFC 1
+
+#define RTE_NET_SOFTNIC 1
+
+#define RTE_NET_TAP 1
+
+#define RTE_NET_THUNDERX 1
+
+#define RTE_NET_TXGBE 1
+
+#define RTE_NET_VDEV_NETVSC 1
+
+#define RTE_NET_VHOST 1
+
+#define RTE_NET_VIRTIO 1
+
+#define RTE_NET_VMXNET3 1
+
+#define RTE_RAW_DPAA2_CMDIF 1
+
+#define RTE_RAW_DPAA2_QDMA 1
+
+#define RTE_RAW_IOAT 1
+
+#define RTE_RAW_NTB 1
+
+#define RTE_RAW_OCTEONTX2_DMA 1
+
+#define RTE_RAW_OCTEONTX2_EP 1
+
+#define RTE_RAW_SKELETON 1
+
+#define RTE_REGEX_MLX5 1
+
+#define RTE_REGEX_OCTEONTX2 1
+
+#define RTE_TOOLCHAIN "gcc"
+
+#define RTE_TOOLCHAIN_GCC 1
+
+#define RTE_VDPA_IFC 1
+
+#define RTE_VDPA_MLX5 1
+
+#define RTE_VER_MINOR 0
+
+#define RTE_VER_MONTH 11
+
+#define RTE_VER_RELEASE 99
+
+#define RTE_VER_SUFFIX ""
+
+#define RTE_VER_YEAR 20
+
+#define RTE_VIRTIO_USER 1
+

contrib/libs/dpdk/drivers/bus/pci/linux/pci.c

@@ -0,0 +1,848 @@
+#include "rte_config.h"
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2014 Intel Corporation
+ */
+
+#include <string.h>
+#include <dirent.h>
+
+#include <rte_log.h>
+#include <rte_bus.h>
+#include <rte_pci.h>
+#include <rte_bus_pci.h>
+#include <rte_malloc.h>
+#include <rte_devargs.h>
+#include <rte_memcpy.h>
+#include <rte_vfio.h>
+
+#include "eal_filesystem.h"
+
+#include "private.h"
+#include "pci_init.h"
+
+/**
+ * @file
+ * PCI probing under linux
+ *
+ * This code is used to simulate a PCI probe by parsing information in sysfs.
+ * When a registered device matches a driver, it is then initialized with
+ * IGB_UIO driver (or doesn't initialize, if the device wasn't bound to it).
+ */
+
+extern struct rte_pci_bus rte_pci_bus;
+
+static int
+pci_get_kernel_driver_by_path(const char *filename, char *dri_name,
+			      size_t len)
+{
+	int count;
+	char path[PATH_MAX];
+	char *name;
+
+	if (!filename || !dri_name)
+		return -1;
+
+	count = readlink(filename, path, PATH_MAX);
+	if (count >= PATH_MAX)
+		return -1;
+
+	/* For device does not have a driver */
+	if (count < 0)
+		return 1;
+
+	path[count] = '\0';
+
+	name = strrchr(path, '/');
+	if (name) {
+		strlcpy(dri_name, name + 1, len);
+		return 0;
+	}
+
+	return -1;
+}
+
+/* Map pci device */
+int
+rte_pci_map_device(struct rte_pci_device *dev)
+{
+	int ret = -1;
+
+	/* try mapping the NIC resources using VFIO if it exists */
+	switch (dev->kdrv) {
+	case RTE_PCI_KDRV_VFIO:
+#ifdef VFIO_PRESENT
+		if (pci_vfio_is_enabled())
+			ret = pci_vfio_map_resource(dev);
+#endif
+		break;
+	case RTE_PCI_KDRV_IGB_UIO:
+	case RTE_PCI_KDRV_UIO_GENERIC:
+		if (rte_eal_using_phys_addrs()) {
+			/* map resources for devices that use uio */
+			ret = pci_uio_map_resource(dev);
+		}
+		break;
+	default:
+		RTE_LOG(DEBUG, EAL,
+			"  Not managed by a supported kernel driver, skipped\n");
+		ret = 1;
+		break;
+	}
+
+	return ret;
+}
+
+/* Unmap pci device */
+void
+rte_pci_unmap_device(struct rte_pci_device *dev)
+{
+	/* try unmapping the NIC resources using VFIO if it exists */
+	switch (dev->kdrv) {
+	case RTE_PCI_KDRV_VFIO:
+#ifdef VFIO_PRESENT
+		if (pci_vfio_is_enabled())
+			pci_vfio_unmap_resource(dev);
+#endif
+		break;
+	case RTE_PCI_KDRV_IGB_UIO:
+	case RTE_PCI_KDRV_UIO_GENERIC:
+		/* unmap resources for devices that use uio */
+		pci_uio_unmap_resource(dev);
+		break;
+	default:
+		RTE_LOG(DEBUG, EAL,
+			"  Not managed by a supported kernel driver, skipped\n");
+		break;
+	}
+}
+
+static int
+find_max_end_va(const struct rte_memseg_list *msl, void *arg)
+{
+	size_t sz = msl->len;
+	void *end_va = RTE_PTR_ADD(msl->base_va, sz);
+	void **max_va = arg;
+
+	if (*max_va < end_va)
+		*max_va = end_va;
+	return 0;
+}
+
+void *
+pci_find_max_end_va(void)
+{
+	void *va = NULL;
+
+	rte_memseg_list_walk(find_max_end_va, &va);
+	return va;
+}
+
+
+/* parse one line of the "resource" sysfs file (note that the 'line'
+ * string is modified)
+ */
+int
+pci_parse_one_sysfs_resource(char *line, size_t len, uint64_t *phys_addr,
+	uint64_t *end_addr, uint64_t *flags)
+{
+	union pci_resource_info {
+		struct {
+			char *phys_addr;
+			char *end_addr;
+			char *flags;
+		};
+		char *ptrs[PCI_RESOURCE_FMT_NVAL];
+	} res_info;
+
+	if (rte_strsplit(line, len, res_info.ptrs, 3, ' ') != 3) {
+		RTE_LOG(ERR, EAL,
+			"%s(): bad resource format\n", __func__);
+		return -1;
+	}
+	errno = 0;
+	*phys_addr = strtoull(res_info.phys_addr, NULL, 16);
+	*end_addr = strtoull(res_info.end_addr, NULL, 16);
+	*flags = strtoull(res_info.flags, NULL, 16);
+	if (errno != 0) {
+		RTE_LOG(ERR, EAL,
+			"%s(): bad resource format\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* parse the "resource" sysfs file */
+static int
+pci_parse_sysfs_resource(const char *filename, struct rte_pci_device *dev)
+{
+	FILE *f;
+	char buf[BUFSIZ];
+	int i;
+	uint64_t phys_addr, end_addr, flags;
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		RTE_LOG(ERR, EAL, "Cannot open sysfs resource\n");
+		return -1;
+	}
+
+	for (i = 0; i<PCI_MAX_RESOURCE; i++) {
+
+		if (fgets(buf, sizeof(buf), f) == NULL) {
+			RTE_LOG(ERR, EAL,
+				"%s(): cannot read resource\n", __func__);
+			goto error;
+		}
+		if (pci_parse_one_sysfs_resource(buf, sizeof(buf), &phys_addr,
+				&end_addr, &flags) < 0)
+			goto error;
+
+		if (flags & IORESOURCE_MEM) {
+			dev->mem_resource[i].phys_addr = phys_addr;
+			dev->mem_resource[i].len = end_addr - phys_addr + 1;
+			/* not mapped for now */
+			dev->mem_resource[i].addr = NULL;
+		}
+	}
+	fclose(f);
+	return 0;
+
+error:
+	fclose(f);
+	return -1;
+}
+
+/* Scan one pci sysfs entry, and fill the devices list from it. */
+static int
+pci_scan_one(const char *dirname, const struct rte_pci_addr *addr)
+{
+	char filename[PATH_MAX];
+	unsigned long tmp;
+	struct rte_pci_device *dev;
+	char driver[PATH_MAX];
+	int ret;
+
+	dev = malloc(sizeof(*dev));
+	if (dev == NULL)
+		return -1;
+
+	memset(dev, 0, sizeof(*dev));
+	dev->device.bus = &rte_pci_bus.bus;
+	dev->addr = *addr;
+
+	/* get vendor id */
+	snprintf(filename, sizeof(filename), "%s/vendor", dirname);
+	if (eal_parse_sysfs_value(filename, &tmp) < 0) {
+		free(dev);
+		return -1;
+	}
+	dev->id.vendor_id = (uint16_t)tmp;
+
+	/* get device id */
+	snprintf(filename, sizeof(filename), "%s/device", dirname);
+	if (eal_parse_sysfs_value(filename, &tmp) < 0) {
+		free(dev);
+		return -1;
+	}
+	dev->id.device_id = (uint16_t)tmp;
+
+	/* get subsystem_vendor id */
+	snprintf(filename, sizeof(filename), "%s/subsystem_vendor",
+		 dirname);
+	if (eal_parse_sysfs_value(filename, &tmp) < 0) {
+		free(dev);
+		return -1;
+	}
+	dev->id.subsystem_vendor_id = (uint16_t)tmp;
+
+	/* get subsystem_device id */
+	snprintf(filename, sizeof(filename), "%s/subsystem_device",
+		 dirname);
+	if (eal_parse_sysfs_value(filename, &tmp) < 0) {
+		free(dev);
+		return -1;
+	}
+	dev->id.subsystem_device_id = (uint16_t)tmp;
+
+	/* get class_id */
+	snprintf(filename, sizeof(filename), "%s/class",
+		 dirname);
+	if (eal_parse_sysfs_value(filename, &tmp) < 0) {
+		free(dev);
+		return -1;
+	}
+	/* the least 24 bits are valid: class, subclass, program interface */
+	dev->id.class_id = (uint32_t)tmp & RTE_CLASS_ANY_ID;
+
+	/* get max_vfs */
+	dev->max_vfs = 0;
+	snprintf(filename, sizeof(filename), "%s/max_vfs", dirname);
+	if (!access(filename, F_OK) &&
+	    eal_parse_sysfs_value(filename, &tmp) == 0)
+		dev->max_vfs = (uint16_t)tmp;
+	else {
+		/* for non igb_uio driver, need kernel version >= 3.8 */
+		snprintf(filename, sizeof(filename),
+			 "%s/sriov_numvfs", dirname);
+		if (!access(filename, F_OK) &&
+		    eal_parse_sysfs_value(filename, &tmp) == 0)
+			dev->max_vfs = (uint16_t)tmp;
+	}
+
+	/* get numa node, default to 0 if not present */
+	snprintf(filename, sizeof(filename), "%s/numa_node",
+		 dirname);
+
+	if (access(filename, F_OK) != -1) {
+		if (eal_parse_sysfs_value(filename, &tmp) == 0)
+			dev->device.numa_node = tmp;
+		else
+			dev->device.numa_node = -1;
+	} else {
+		dev->device.numa_node = 0;
+	}
+
+	pci_name_set(dev);
+
+	/* parse resources */
+	snprintf(filename, sizeof(filename), "%s/resource", dirname);
+	if (pci_parse_sysfs_resource(filename, dev) < 0) {
+		RTE_LOG(ERR, EAL, "%s(): cannot parse resource\n", __func__);
+		free(dev);
+		return -1;
+	}
+
+	/* parse driver */
+	snprintf(filename, sizeof(filename), "%s/driver", dirname);
+	ret = pci_get_kernel_driver_by_path(filename, driver, sizeof(driver));
+	if (ret < 0) {
+		RTE_LOG(ERR, EAL, "Fail to get kernel driver\n");
+		free(dev);
+		return -1;
+	}
+
+	if (!ret) {
+		if (!strcmp(driver, "vfio-pci"))
+			dev->kdrv = RTE_PCI_KDRV_VFIO;
+		else if (!strcmp(driver, "igb_uio"))
+			dev->kdrv = RTE_PCI_KDRV_IGB_UIO;
+		else if (!strcmp(driver, "uio_pci_generic"))
+			dev->kdrv = RTE_PCI_KDRV_UIO_GENERIC;
+		else
+			dev->kdrv = RTE_PCI_KDRV_UNKNOWN;
+	} else {
+		dev->kdrv = RTE_PCI_KDRV_NONE;
+		return 0;
+	}
+	/* device is valid, add in list (sorted) */
+	if (TAILQ_EMPTY(&rte_pci_bus.device_list)) {
+		rte_pci_add_device(dev);
+	} else {
+		struct rte_pci_device *dev2;
+		int ret;
+
+		TAILQ_FOREACH(dev2, &rte_pci_bus.device_list, next) {
+			ret = rte_pci_addr_cmp(&dev->addr, &dev2->addr);
+			if (ret > 0)
+				continue;
+
+			if (ret < 0) {
+				rte_pci_insert_device(dev2, dev);
+			} else { /* already registered */
+				if (!rte_dev_is_probed(&dev2->device)) {
+					dev2->kdrv = dev->kdrv;
+					dev2->max_vfs = dev->max_vfs;
+					dev2->id = dev->id;
+					pci_name_set(dev2);
+					memmove(dev2->mem_resource,
+						dev->mem_resource,
+						sizeof(dev->mem_resource));
+				} else {
+					/**
+					 * If device is plugged and driver is
+					 * probed already, (This happens when
+					 * we call rte_dev_probe which will
+					 * scan all device on the bus) we don't
+					 * need to do anything here unless...
+					 **/
+					if (dev2->kdrv != dev->kdrv ||
+						dev2->max_vfs != dev->max_vfs ||
+						memcmp(&dev2->id, &dev->id, sizeof(dev2->id)))
+						/*
+						 * This should not happens.
+						 * But it is still possible if
+						 * we unbind a device from
+						 * vfio or uio before hotplug
+						 * remove and rebind it with
+						 * a different configure.
+						 * So we just print out the
+						 * error as an alarm.
+						 */
+						RTE_LOG(ERR, EAL, "Unexpected device scan at %s!\n",
+							filename);
+					else if (dev2->device.devargs !=
+						 dev->device.devargs) {
+						rte_devargs_remove(dev2->device.devargs);
+						pci_name_set(dev2);
+					}
+				}
+				free(dev);
+			}
+			return 0;
+		}
+
+		rte_pci_add_device(dev);
+	}
+
+	return 0;
+}
+
+/*
+ * split up a pci address into its constituent parts.
+ */
+static int
+parse_pci_addr_format(const char *buf, int bufsize, struct rte_pci_addr *addr)
+{
+	/* first split on ':' */
+	union splitaddr {
+		struct {
+			char *domain;
+			char *bus;
+			char *devid;
+			char *function;
+		};
+		char *str[PCI_FMT_NVAL]; /* last element-separator is "." not ":" */
+	} splitaddr;
+
+	char *buf_copy = strndup(buf, bufsize);
+	if (buf_copy == NULL)
+		return -1;
+
+	if (rte_strsplit(buf_copy, bufsize, splitaddr.str, PCI_FMT_NVAL, ':')
+			!= PCI_FMT_NVAL - 1)
+		goto error;
+	/* final split is on '.' between devid and function */
+	splitaddr.function = strchr(splitaddr.devid,'.');
+	if (splitaddr.function == NULL)
+		goto error;
+	*splitaddr.function++ = '\0';
+
+	/* now convert to int values */
+	errno = 0;
+	addr->domain = strtoul(splitaddr.domain, NULL, 16);
+	addr->bus = strtoul(splitaddr.bus, NULL, 16);
+	addr->devid = strtoul(splitaddr.devid, NULL, 16);
+	addr->function = strtoul(splitaddr.function, NULL, 10);
+	if (errno != 0)
+		goto error;
+
+	free(buf_copy); /* free the copy made with strdup */
+	return 0;
+error:
+	free(buf_copy);
+	return -1;
+}
+
+/*
+ * Scan the content of the PCI bus, and the devices in the devices
+ * list
+ */
+int
+rte_pci_scan(void)
+{
+	struct dirent *e;
+	DIR *dir;
+	char dirname[PATH_MAX];
+	struct rte_pci_addr addr;
+
+	/* for debug purposes, PCI can be disabled */
+	if (!rte_eal_has_pci())
+		return 0;
+
+#ifdef VFIO_PRESENT
+	if (!pci_vfio_is_enabled())
+		RTE_LOG(DEBUG, EAL, "VFIO PCI modules not loaded\n");
+#endif
+
+	dir = opendir(rte_pci_get_sysfs_path());
+	if (dir == NULL) {
+		RTE_LOG(ERR, EAL, "%s(): opendir failed: %s\n",
+			__func__, strerror(errno));
+		return -1;
+	}
+
+	while ((e = readdir(dir)) != NULL) {
+		if (e->d_name[0] == '.')
+			continue;
+
+		if (parse_pci_addr_format(e->d_name, sizeof(e->d_name), &addr) != 0)
+			continue;
+
+		if (rte_pci_ignore_device(&addr))
+			continue;
+
+		snprintf(dirname, sizeof(dirname), "%s/%s",
+				rte_pci_get_sysfs_path(), e->d_name);
+
+		if (pci_scan_one(dirname, &addr) < 0)
+			goto error;
+	}
+	closedir(dir);
+	return 0;
+
+error:
+	closedir(dir);
+	return -1;
+}
+
+#if defined(RTE_ARCH_X86)
+bool
+pci_device_iommu_support_va(const struct rte_pci_device *dev)
+{
+#define VTD_CAP_MGAW_SHIFT	16
+#define VTD_CAP_MGAW_MASK	(0x3fULL << VTD_CAP_MGAW_SHIFT)
+	const struct rte_pci_addr *addr = &dev->addr;
+	char filename[PATH_MAX];
+	FILE *fp;
+	uint64_t mgaw, vtd_cap_reg = 0;
+
+	snprintf(filename, sizeof(filename),
+		 "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap",
+		 rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid,
+		 addr->function);
+
+	fp = fopen(filename, "r");
+	if (fp == NULL) {
+		/* We don't have an Intel IOMMU, assume VA supported */
+		if (errno == ENOENT)
+			return true;
+
+		RTE_LOG(ERR, EAL, "%s(): can't open %s: %s\n",
+			__func__, filename, strerror(errno));
+		return false;
+	}
+
+	/* We have an Intel IOMMU */
+	if (fscanf(fp, "%" PRIx64, &vtd_cap_reg) != 1) {
+		RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename);
+		fclose(fp);
+		return false;
+	}
+
+	fclose(fp);
+
+	mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;
+
+	/*
+	 * Assuming there is no limitation by now. We can not know at this point
+	 * because the memory has not been initialized yet. Setting the dma mask
+	 * will force a check once memory initialization is done. We can not do
+	 * a fallback to IOVA PA now, but if the dma check fails, the error
+	 * message should advice for using '--iova-mode pa' if IOVA VA is the
+	 * current mode.
+	 */
+	rte_mem_set_dma_mask(mgaw);
+	return true;
+}
+#elif defined(RTE_ARCH_PPC_64)
+bool
+pci_device_iommu_support_va(__rte_unused const struct rte_pci_device *dev)
+{
+	/*
+	 * IOMMU is always present on a PowerNV host (IOMMUv2).
+	 * IOMMU is also present in a KVM/QEMU VM (IOMMUv1) but is not
+	 * currently supported by DPDK. Test for our current environment
+	 * and report VA support as appropriate.
+	 */
+
+	char *line = NULL;
+	size_t len = 0;
+	char filename[PATH_MAX] = "/proc/cpuinfo";
+	FILE *fp = fopen(filename, "r");
+	bool ret = false;
+
+	if (fp == NULL) {
+		RTE_LOG(ERR, EAL, "%s(): can't open %s: %s\n",
+			__func__, filename, strerror(errno));
+		return ret;
+	}
+
+	/* Check for a PowerNV platform */
+	while (getline(&line, &len, fp) != -1) {
+		if (strstr(line, "platform") != NULL)
+			continue;
+
+		if (strstr(line, "PowerNV") != NULL) {
+			RTE_LOG(DEBUG, EAL, "Running on a PowerNV system\n");
+			ret = true;
+			break;
+		}
+	}
+
+	free(line);
+	fclose(fp);
+	return ret;
+}
+#else
+bool
+pci_device_iommu_support_va(__rte_unused const struct rte_pci_device *dev)
+{
+	return true;
+}
+#endif
+
+enum rte_iova_mode
+pci_device_iova_mode(const struct rte_pci_driver *pdrv,
+		     const struct rte_pci_device *pdev)
+{
+	enum rte_iova_mode iova_mode = RTE_IOVA_DC;
+
+	switch (pdev->kdrv) {
+	case RTE_PCI_KDRV_VFIO: {
+#ifdef VFIO_PRESENT
+		static int is_vfio_noiommu_enabled = -1;
+
+		if (is_vfio_noiommu_enabled == -1) {
+			if (rte_vfio_noiommu_is_enabled() == 1)
+				is_vfio_noiommu_enabled = 1;
+			else
+				is_vfio_noiommu_enabled = 0;
+		}
+		if (is_vfio_noiommu_enabled != 0)
+			iova_mode = RTE_IOVA_PA;
+		else if ((pdrv->drv_flags & RTE_PCI_DRV_NEED_IOVA_AS_VA) != 0)
+			iova_mode = RTE_IOVA_VA;
+#endif
+		break;
+	}
+
+	case RTE_PCI_KDRV_IGB_UIO:
+	case RTE_PCI_KDRV_UIO_GENERIC:
+		iova_mode = RTE_IOVA_PA;
+		break;
+
+	default:
+		if ((pdrv->drv_flags & RTE_PCI_DRV_NEED_IOVA_AS_VA) != 0)
+			iova_mode = RTE_IOVA_VA;
+		break;
+	}
+	return iova_mode;
+}
+
+/* Read PCI config space. */
+int rte_pci_read_config(const struct rte_pci_device *device,
+		void *buf, size_t len, off_t offset)
+{
+	char devname[RTE_DEV_NAME_MAX_LEN] = "";
+	const struct rte_intr_handle *intr_handle = &device->intr_handle;
+
+	switch (device->kdrv) {
+	case RTE_PCI_KDRV_IGB_UIO:
+	case RTE_PCI_KDRV_UIO_GENERIC:
+		return pci_uio_read_config(intr_handle, buf, len, offset);
+#ifdef VFIO_PRESENT
+	case RTE_PCI_KDRV_VFIO:
+		return pci_vfio_read_config(intr_handle, buf, len, offset);
+#endif
+	default:
+		rte_pci_device_name(&device->addr, devname,
+				    RTE_DEV_NAME_MAX_LEN);
+		RTE_LOG(ERR, EAL,
+			"Unknown driver type for %s\n", devname);
+		return -1;
+	}
+}
+
+/* Write PCI config space. */
+int rte_pci_write_config(const struct rte_pci_device *device,
+		const void *buf, size_t len, off_t offset)
+{
+	char devname[RTE_DEV_NAME_MAX_LEN] = "";
+	const struct rte_intr_handle *intr_handle = &device->intr_handle;
+
+	switch (device->kdrv) {
+	case RTE_PCI_KDRV_IGB_UIO:
+	case RTE_PCI_KDRV_UIO_GENERIC:
+		return pci_uio_write_config(intr_handle, buf, len, offset);
+#ifdef VFIO_PRESENT
+	case RTE_PCI_KDRV_VFIO:
+		return pci_vfio_write_config(intr_handle, buf, len, offset);
+#endif
+	default:
+		rte_pci_device_name(&device->addr, devname,
+				    RTE_DEV_NAME_MAX_LEN);
+		RTE_LOG(ERR, EAL,
+			"Unknown driver type for %s\n", devname);
+		return -1;
+	}
+}
+
+#if defined(RTE_ARCH_X86)
+static int
+pci_ioport_map(struct rte_pci_device *dev, int bar __rte_unused,
+		struct rte_pci_ioport *p)
+{
+	uint16_t start, end;
+	FILE *fp;
+	char *line = NULL;
+	char pci_id[16];
+	int found = 0;
+	size_t linesz;
+
+	if (rte_eal_iopl_init() != 0) {
+		RTE_LOG(ERR, EAL, "%s(): insufficient ioport permissions for PCI device %s\n",
+			__func__, dev->name);
+		return -1;
+	}
+
+	snprintf(pci_id, sizeof(pci_id), PCI_PRI_FMT,
+		 dev->addr.domain, dev->addr.bus,
+		 dev->addr.devid, dev->addr.function);
+
+	fp = fopen("/proc/ioports", "r");
+	if (fp == NULL) {
+		RTE_LOG(ERR, EAL, "%s(): can't open ioports\n", __func__);
+		return -1;
+	}
+
+	while (getdelim(&line, &linesz, '\n', fp) > 0) {
+		char *ptr = line;
+		char *left;
+		int n;
+
+		n = strcspn(ptr, ":");
+		ptr[n] = 0;
+		left = &ptr[n + 1];
+
+		while (*left && isspace(*left))
+			left++;
+
+		if (!strncmp(left, pci_id, strlen(pci_id))) {
+			found = 1;
+
+			while (*ptr && isspace(*ptr))
+				ptr++;
+
+			sscanf(ptr, "%04hx-%04hx", &start, &end);
+
+			break;
+		}
+	}
+
+	free(line);
+	fclose(fp);
+
+	if (!found)
+		return -1;
+
+	p->base = start;
+	RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%x\n", start);
+
+	return 0;
+}
+#endif
+
+int
+rte_pci_ioport_map(struct rte_pci_device *dev, int bar,
+		struct rte_pci_ioport *p)
+{
+	int ret = -1;
+
+	switch (dev->kdrv) {
+#ifdef VFIO_PRESENT
+	case RTE_PCI_KDRV_VFIO:
+		if (pci_vfio_is_enabled())
+			ret = pci_vfio_ioport_map(dev, bar, p);
+		break;
+#endif
+	case RTE_PCI_KDRV_IGB_UIO:
+		ret = pci_uio_ioport_map(dev, bar, p);
+		break;
+	case RTE_PCI_KDRV_UIO_GENERIC:
+#if defined(RTE_ARCH_X86)
+		ret = pci_ioport_map(dev, bar, p);
+#else
+		ret = pci_uio_ioport_map(dev, bar, p);
+#endif
+		break;
+	default:
+		break;
+	}
+
+	if (!ret)
+		p->dev = dev;
+
+	return ret;
+}
+
+void
+rte_pci_ioport_read(struct rte_pci_ioport *p,
+		void *data, size_t len, off_t offset)
+{
+	switch (p->dev->kdrv) {
+#ifdef VFIO_PRESENT
+	case RTE_PCI_KDRV_VFIO:
+		pci_vfio_ioport_read(p, data, len, offset);
+		break;
+#endif
+	case RTE_PCI_KDRV_IGB_UIO:
+		pci_uio_ioport_read(p, data, len, offset);
+		break;
+	case RTE_PCI_KDRV_UIO_GENERIC:
+		pci_uio_ioport_read(p, data, len, offset);
+		break;
+	default:
+		break;
+	}
+}
+
+void
+rte_pci_ioport_write(struct rte_pci_ioport *p,
+		const void *data, size_t len, off_t offset)
+{
+	switch (p->dev->kdrv) {
+#ifdef VFIO_PRESENT
+	case RTE_PCI_KDRV_VFIO:
+		pci_vfio_ioport_write(p, data, len, offset);
+		break;
+#endif
+	case RTE_PCI_KDRV_IGB_UIO:
+		pci_uio_ioport_write(p, data, len, offset);
+		break;
+	case RTE_PCI_KDRV_UIO_GENERIC:
+		pci_uio_ioport_write(p, data, len, offset);
+		break;
+	default:
+		break;
+	}
+}
+
+int
+rte_pci_ioport_unmap(struct rte_pci_ioport *p)
+{
+	int ret = -1;
+
+	switch (p->dev->kdrv) {
+#ifdef VFIO_PRESENT
+	case RTE_PCI_KDRV_VFIO:
+		if (pci_vfio_is_enabled())
+			ret = pci_vfio_ioport_unmap(p);
+		break;
+#endif
+	case RTE_PCI_KDRV_IGB_UIO:
+		ret = pci_uio_ioport_unmap(p);
+		break;
+	case RTE_PCI_KDRV_UIO_GENERIC:
+#if defined(RTE_ARCH_X86)
+		ret = 0;
+#else
+		ret = pci_uio_ioport_unmap(p);
+#endif
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}

contrib/libs/dpdk/drivers/bus/pci/linux/pci_init.h

@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2014 Intel Corporation
+ */
+
+#ifndef EAL_PCI_INIT_H_
+#define EAL_PCI_INIT_H_
+
+#include <rte_vfio.h>
+
+#include "private.h"
+
+/** IO resource type: */
+#define IORESOURCE_IO         0x00000100
+#define IORESOURCE_MEM        0x00000200
+
+/*
+ * Helper function to map PCI resources right after hugepages in virtual memory
+ */
+extern void *pci_map_addr;
+void *pci_find_max_end_va(void);
+
+/* parse one line of the "resource" sysfs file (note that the 'line'
+ * string is modified)
+ */
+int pci_parse_one_sysfs_resource(char *line, size_t len, uint64_t *phys_addr,
+	uint64_t *end_addr, uint64_t *flags);
+
+int pci_uio_alloc_resource(struct rte_pci_device *dev,
+		struct mapped_pci_resource **uio_res);
+void pci_uio_free_resource(struct rte_pci_device *dev,
+		struct mapped_pci_resource *uio_res);
+int pci_uio_map_resource_by_index(struct rte_pci_device *dev, int res_idx,
+		struct mapped_pci_resource *uio_res, int map_idx);
+
+int pci_uio_read_config(const struct rte_intr_handle *intr_handle,
+			void *buf, size_t len, off_t offs);
+int pci_uio_write_config(const struct rte_intr_handle *intr_handle,
+			 const void *buf, size_t len, off_t offs);
+
+int pci_uio_ioport_map(struct rte_pci_device *dev, int bar,
+		       struct rte_pci_ioport *p);
+void pci_uio_ioport_read(struct rte_pci_ioport *p,
+			 void *data, size_t len, off_t offset);
+void pci_uio_ioport_write(struct rte_pci_ioport *p,
+			  const void *data, size_t len, off_t offset);
+int pci_uio_ioport_unmap(struct rte_pci_ioport *p);
+
+#ifdef VFIO_PRESENT
+
+#ifdef PCI_MSIX_TABLE_BIR
+#define RTE_PCI_MSIX_TABLE_BIR    PCI_MSIX_TABLE_BIR
+#else
+#define RTE_PCI_MSIX_TABLE_BIR    0x7
+#endif
+
+#ifdef PCI_MSIX_TABLE_OFFSET
+#define RTE_PCI_MSIX_TABLE_OFFSET PCI_MSIX_TABLE_OFFSET
+#else
+#define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8
+#endif
+
+#ifdef PCI_MSIX_FLAGS_QSIZE
+#define RTE_PCI_MSIX_FLAGS_QSIZE  PCI_MSIX_FLAGS_QSIZE
+#else
+#define RTE_PCI_MSIX_FLAGS_QSIZE  0x07ff
+#endif
+
+/* access config space */
+int pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
+			 void *buf, size_t len, off_t offs);
+int pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
+			  const void *buf, size_t len, off_t offs);
+
+int pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
+		        struct rte_pci_ioport *p);
+void pci_vfio_ioport_read(struct rte_pci_ioport *p,
+			  void *data, size_t len, off_t offset);
+void pci_vfio_ioport_write(struct rte_pci_ioport *p,
+			   const void *data, size_t len, off_t offset);
+int pci_vfio_ioport_unmap(struct rte_pci_ioport *p);
+
+/* map/unmap VFIO resource prototype */
+int pci_vfio_map_resource(struct rte_pci_device *dev);
+int pci_vfio_unmap_resource(struct rte_pci_device *dev);
+
+int pci_vfio_is_enabled(void);
+
+#endif
+
+#endif /* EAL_PCI_INIT_H_ */

contrib/libs/dpdk/drivers/bus/pci/linux/pci_uio.c

@@ -0,0 +1,571 @@
+#include "rte_config.h"
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2014 Intel Corporation
+ */
+
+#include <string.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <dirent.h>
+#include <inttypes.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+#include <sys/sysmacros.h>
+#include <linux/pci_regs.h>
+
+#if defined(RTE_ARCH_X86)
+#include <sys/io.h>
+#endif
+
+#include <rte_string_fns.h>
+#include <rte_log.h>
+#include <rte_pci.h>
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_malloc.h>
+
+#include "eal_filesystem.h"
+#include "pci_init.h"
+#include "private.h"
+
+void *pci_map_addr = NULL;
+
+#define OFF_MAX              ((uint64_t)(off_t)-1)
+
+int
+pci_uio_read_config(const struct rte_intr_handle *intr_handle,
+		    void *buf, size_t len, off_t offset)
+{
+	return pread(intr_handle->uio_cfg_fd, buf, len, offset);
+}
+
+int
+pci_uio_write_config(const struct rte_intr_handle *intr_handle,
+		     const void *buf, size_t len, off_t offset)
+{
+	return pwrite(intr_handle->uio_cfg_fd, buf, len, offset);
+}
+
+static int
+pci_uio_set_bus_master(int dev_fd)
+{
+	uint16_t reg;
+	int ret;
+
+	ret = pread(dev_fd, &reg, sizeof(reg), PCI_COMMAND);
+	if (ret != sizeof(reg)) {
+		RTE_LOG(ERR, EAL,
+			"Cannot read command from PCI config space!\n");
+		return -1;
+	}
+
+	/* return if bus mastering is already on */
+	if (reg & PCI_COMMAND_MASTER)
+		return 0;
+
+	reg |= PCI_COMMAND_MASTER;
+
+	ret = pwrite(dev_fd, &reg, sizeof(reg), PCI_COMMAND);
+	if (ret != sizeof(reg)) {
+		RTE_LOG(ERR, EAL,
+			"Cannot write command to PCI config space!\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+static int
+pci_mknod_uio_dev(const char *sysfs_uio_path, unsigned uio_num)
+{
+	FILE *f;
+	char filename[PATH_MAX];
+	int ret;
+	unsigned major, minor;
+	dev_t dev;
+
+	/* get the name of the sysfs file that contains the major and minor
+	 * of the uio device and read its content */
+	snprintf(filename, sizeof(filename), "%s/dev", sysfs_uio_path);
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		RTE_LOG(ERR, EAL, "%s(): cannot open sysfs to get major:minor\n",
+			__func__);
+		return -1;
+	}
+
+	ret = fscanf(f, "%u:%u", &major, &minor);
+	if (ret != 2) {
+		RTE_LOG(ERR, EAL, "%s(): cannot parse sysfs to get major:minor\n",
+			__func__);
+		fclose(f);
+		return -1;
+	}
+	fclose(f);
+
+	/* create the char device "mknod /dev/uioX c major minor" */
+	snprintf(filename, sizeof(filename), "/dev/uio%u", uio_num);
+	dev = makedev(major, minor);
+	ret = mknod(filename, S_IFCHR | S_IRUSR | S_IWUSR, dev);
+	if (ret != 0) {
+		RTE_LOG(ERR, EAL, "%s(): mknod() failed %s\n",
+			__func__, strerror(errno));
+		return -1;
+	}
+
+	return ret;
+}
+
+/*
+ * Return the uioX char device used for a pci device. On success, return
+ * the UIO number and fill dstbuf string with the path of the device in
+ * sysfs. On error, return a negative value. In this case dstbuf is
+ * invalid.
+ */
+static int
+pci_get_uio_dev(struct rte_pci_device *dev, char *dstbuf,
+			   unsigned int buflen, int create)
+{
+	struct rte_pci_addr *loc = &dev->addr;
+	int uio_num = -1;
+	struct dirent *e;
+	DIR *dir;
+	char dirname[PATH_MAX];
+
+	/* depending on kernel version, uio can be located in uio/uioX
+	 * or uio:uioX */
+
+	snprintf(dirname, sizeof(dirname),
+			"%s/" PCI_PRI_FMT "/uio", rte_pci_get_sysfs_path(),
+			loc->domain, loc->bus, loc->devid, loc->function);
+
+	dir = opendir(dirname);
+	if (dir == NULL) {
+		/* retry with the parent directory */
+		snprintf(dirname, sizeof(dirname),
+				"%s/" PCI_PRI_FMT, rte_pci_get_sysfs_path(),
+				loc->domain, loc->bus, loc->devid, loc->function);
+		dir = opendir(dirname);
+
+		if (dir == NULL) {
+			RTE_LOG(ERR, EAL, "Cannot opendir %s\n", dirname);
+			return -1;
+		}
+	}
+
+	/* take the first file starting with "uio" */
+	while ((e = readdir(dir)) != NULL) {
+		/* format could be uio%d ...*/
+		int shortprefix_len = sizeof("uio") - 1;
+		/* ... or uio:uio%d */
+		int longprefix_len = sizeof("uio:uio") - 1;
+		char *endptr;
+
+		if (strncmp(e->d_name, "uio", 3) != 0)
+			continue;
+
+		/* first try uio%d */
+		errno = 0;
+		uio_num = strtoull(e->d_name + shortprefix_len, &endptr, 10);
+		if (errno == 0 && endptr != (e->d_name + shortprefix_len)) {
+			snprintf(dstbuf, buflen, "%s/uio%u", dirname, uio_num);
+			break;
+		}
+
+		/* then try uio:uio%d */
+		errno = 0;
+		uio_num = strtoull(e->d_name + longprefix_len, &endptr, 10);
+		if (errno == 0 && endptr != (e->d_name + longprefix_len)) {
+			snprintf(dstbuf, buflen, "%s/uio:uio%u", dirname, uio_num);
+			break;
+		}
+	}
+	closedir(dir);
+
+	/* No uio resource found */
+	if (e == NULL)
+		return -1;
+
+	/* create uio device if we've been asked to */
+	if (rte_eal_create_uio_dev() && create &&
+			pci_mknod_uio_dev(dstbuf, uio_num) < 0)
+		RTE_LOG(WARNING, EAL, "Cannot create /dev/uio%u\n", uio_num);
+
+	return uio_num;
+}
+
+void
+pci_uio_free_resource(struct rte_pci_device *dev,
+		struct mapped_pci_resource *uio_res)
+{
+	rte_free(uio_res);
+
+	if (dev->intr_handle.uio_cfg_fd >= 0) {
+		close(dev->intr_handle.uio_cfg_fd);
+		dev->intr_handle.uio_cfg_fd = -1;
+	}
+	if (dev->intr_handle.fd >= 0) {
+		close(dev->intr_handle.fd);
+		dev->intr_handle.fd = -1;
+		dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
+	}
+}
+
+int
+pci_uio_alloc_resource(struct rte_pci_device *dev,
+		struct mapped_pci_resource **uio_res)
+{
+	char dirname[PATH_MAX];
+	char cfgname[PATH_MAX];
+	char devname[PATH_MAX]; /* contains the /dev/uioX */
+	int uio_num;
+	struct rte_pci_addr *loc;
+
+	loc = &dev->addr;
+
+	/* find uio resource */
+	uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname), 1);
+	if (uio_num < 0) {
+		RTE_LOG(WARNING, EAL, "  "PCI_PRI_FMT" not managed by UIO driver, "
+				"skipping\n", loc->domain, loc->bus, loc->devid, loc->function);
+		return 1;
+	}
+	snprintf(devname, sizeof(devname), "/dev/uio%u", uio_num);
+
+	/* save fd if in primary process */
+	dev->intr_handle.fd = open(devname, O_RDWR);
+	if (dev->intr_handle.fd < 0) {
+		RTE_LOG(ERR, EAL, "Cannot open %s: %s\n",
+			devname, strerror(errno));
+		goto error;
+	}
+
+	snprintf(cfgname, sizeof(cfgname),
+			"/sys/class/uio/uio%u/device/config", uio_num);
+	dev->intr_handle.uio_cfg_fd = open(cfgname, O_RDWR);
+	if (dev->intr_handle.uio_cfg_fd < 0) {
+		RTE_LOG(ERR, EAL, "Cannot open %s: %s\n",
+			cfgname, strerror(errno));
+		goto error;
+	}
+
+	if (dev->kdrv == RTE_PCI_KDRV_IGB_UIO)
+		dev->intr_handle.type = RTE_INTR_HANDLE_UIO;
+	else {
+		dev->intr_handle.type = RTE_INTR_HANDLE_UIO_INTX;
+
+		/* set bus master that is not done by uio_pci_generic */
+		if (pci_uio_set_bus_master(dev->intr_handle.uio_cfg_fd)) {
+			RTE_LOG(ERR, EAL, "Cannot set up bus mastering!\n");
+			goto error;
+		}
+	}
+
+	/* allocate the mapping details for secondary processes*/
+	*uio_res = rte_zmalloc("UIO_RES", sizeof(**uio_res), 0);
+	if (*uio_res == NULL) {
+		RTE_LOG(ERR, EAL,
+			"%s(): cannot store uio mmap details\n", __func__);
+		goto error;
+	}
+
+	strlcpy((*uio_res)->path, devname, sizeof((*uio_res)->path));
+	memcpy(&(*uio_res)->pci_addr, &dev->addr, sizeof((*uio_res)->pci_addr));
+
+	return 0;
+
+error:
+	pci_uio_free_resource(dev, *uio_res);
+	return -1;
+}
+
+int
+pci_uio_map_resource_by_index(struct rte_pci_device *dev, int res_idx,
+		struct mapped_pci_resource *uio_res, int map_idx)
+{
+	int fd = -1;
+	char devname[PATH_MAX];
+	void *mapaddr;
+	struct rte_pci_addr *loc;
+	struct pci_map *maps;
+	int wc_activate = 0;
+
+	if (dev->driver != NULL)
+		wc_activate = dev->driver->drv_flags & RTE_PCI_DRV_WC_ACTIVATE;
+
+	loc = &dev->addr;
+	maps = uio_res->maps;
+
+	/* allocate memory to keep path */
+	maps[map_idx].path = rte_malloc(NULL, sizeof(devname), 0);
+	if (maps[map_idx].path == NULL) {
+		RTE_LOG(ERR, EAL, "Cannot allocate memory for path: %s\n",
+				strerror(errno));
+		return -1;
+	}
+
+	/*
+	 * open resource file, to mmap it
+	 */
+	if (wc_activate) {
+		/* update devname for mmap  */
+		snprintf(devname, sizeof(devname),
+			"%s/" PCI_PRI_FMT "/resource%d_wc",
+			rte_pci_get_sysfs_path(),
+			loc->domain, loc->bus, loc->devid,
+			loc->function, res_idx);
+
+		fd = open(devname, O_RDWR);
+		if (fd < 0 && errno != ENOENT) {
+			RTE_LOG(INFO, EAL, "%s cannot be mapped. "
+				"Fall-back to non prefetchable mode.\n",
+				devname);
+		}
+	}
+
+	if (!wc_activate || fd < 0) {
+		snprintf(devname, sizeof(devname),
+			"%s/" PCI_PRI_FMT "/resource%d",
+			rte_pci_get_sysfs_path(),
+			loc->domain, loc->bus, loc->devid,
+			loc->function, res_idx);
+
+		/* then try to map resource file */
+		fd = open(devname, O_RDWR);
+		if (fd < 0) {
+			RTE_LOG(ERR, EAL, "Cannot open %s: %s\n",
+				devname, strerror(errno));
+			goto error;
+		}
+	}
+
+	/* try mapping somewhere close to the end of hugepages */
+	if (pci_map_addr == NULL)
+		pci_map_addr = pci_find_max_end_va();
+
+	mapaddr = pci_map_resource(pci_map_addr, fd, 0,
+			(size_t)dev->mem_resource[res_idx].len, 0);
+	close(fd);
+	if (mapaddr == NULL)
+		goto error;
+
+	pci_map_addr = RTE_PTR_ADD(mapaddr,
+			(size_t)dev->mem_resource[res_idx].len);
+
+	pci_map_addr = RTE_PTR_ALIGN(pci_map_addr, sysconf(_SC_PAGE_SIZE));
+
+	maps[map_idx].phaddr = dev->mem_resource[res_idx].phys_addr;
+	maps[map_idx].size = dev->mem_resource[res_idx].len;
+	maps[map_idx].addr = mapaddr;
+	maps[map_idx].offset = 0;
+	strcpy(maps[map_idx].path, devname);
+	dev->mem_resource[res_idx].addr = mapaddr;
+
+	return 0;
+
+error:
+	rte_free(maps[map_idx].path);
+	return -1;
+}
+
+#if defined(RTE_ARCH_X86)
+int
+pci_uio_ioport_map(struct rte_pci_device *dev, int bar,
+		   struct rte_pci_ioport *p)
+{
+	char dirname[PATH_MAX];
+	char filename[PATH_MAX];
+	int uio_num;
+	unsigned long start;
+
+	if (rte_eal_iopl_init() != 0) {
+		RTE_LOG(ERR, EAL, "%s(): insufficient ioport permissions for PCI device %s\n",
+			__func__, dev->name);
+		return -1;
+	}
+
+	uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname), 0);
+	if (uio_num < 0)
+		return -1;
+
+	/* get portio start */
+	snprintf(filename, sizeof(filename),
+		 "%s/portio/port%d/start", dirname, bar);
+	if (eal_parse_sysfs_value(filename, &start) < 0) {
+		RTE_LOG(ERR, EAL, "%s(): cannot parse portio start\n",
+			__func__);
+		return -1;
+	}
+	/* ensure we don't get anything funny here, read/write will cast to
+	 * uin16_t */
+	if (start > UINT16_MAX)
+		return -1;
+
+	/* FIXME only for primary process ? */
+	if (dev->intr_handle.type == RTE_INTR_HANDLE_UNKNOWN) {
+
+		snprintf(filename, sizeof(filename), "/dev/uio%u", uio_num);
+		dev->intr_handle.fd = open(filename, O_RDWR);
+		if (dev->intr_handle.fd < 0) {
+			RTE_LOG(ERR, EAL, "Cannot open %s: %s\n",
+				filename, strerror(errno));
+			return -1;
+		}
+		dev->intr_handle.type = RTE_INTR_HANDLE_UIO;
+	}
+
+	RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%lx\n", start);
+
+	p->base = start;
+	p->len = 0;
+	return 0;
+}
+#else
+int
+pci_uio_ioport_map(struct rte_pci_device *dev, int bar,
+		   struct rte_pci_ioport *p)
+{
+	FILE *f;
+	char buf[BUFSIZ];
+	char filename[PATH_MAX];
+	uint64_t phys_addr, end_addr, flags;
+	int fd, i;
+	void *addr;
+
+	/* open and read addresses of the corresponding resource in sysfs */
+	snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/resource",
+		rte_pci_get_sysfs_path(), dev->addr.domain, dev->addr.bus,
+		dev->addr.devid, dev->addr.function);
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		RTE_LOG(ERR, EAL, "Cannot open sysfs resource: %s\n",
+			strerror(errno));
+		return -1;
+	}
+	for (i = 0; i < bar + 1; i++) {
+		if (fgets(buf, sizeof(buf), f) == NULL) {
+			RTE_LOG(ERR, EAL, "Cannot read sysfs resource\n");
+			goto error;
+		}
+	}
+	if (pci_parse_one_sysfs_resource(buf, sizeof(buf), &phys_addr,
+			&end_addr, &flags) < 0)
+		goto error;
+	if ((flags & IORESOURCE_IO) == 0) {
+		RTE_LOG(ERR, EAL, "BAR %d is not an IO resource\n", bar);
+		goto error;
+	}
+	snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/resource%d",
+		rte_pci_get_sysfs_path(), dev->addr.domain, dev->addr.bus,
+		dev->addr.devid, dev->addr.function, bar);
+
+	/* mmap the pci resource */
+	fd = open(filename, O_RDWR);
+	if (fd < 0) {
+		RTE_LOG(ERR, EAL, "Cannot open %s: %s\n", filename,
+			strerror(errno));
+		goto error;
+	}
+	addr = mmap(NULL, end_addr + 1, PROT_READ | PROT_WRITE,
+		MAP_SHARED, fd, 0);
+	close(fd);
+	if (addr == MAP_FAILED) {
+		RTE_LOG(ERR, EAL, "Cannot mmap IO port resource: %s\n",
+			strerror(errno));
+		goto error;
+	}
+
+	/* strangely, the base address is mmap addr + phys_addr */
+	p->base = (uintptr_t)addr + phys_addr;
+	p->len = end_addr + 1;
+	RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%"PRIx64"\n", p->base);
+	fclose(f);
+
+	return 0;
+
+error:
+	fclose(f);
+	return -1;
+}
+#endif
+
+void
+pci_uio_ioport_read(struct rte_pci_ioport *p,
+		    void *data, size_t len, off_t offset)
+{
+	uint8_t *d;
+	int size;
+	uintptr_t reg = p->base + offset;
+
+	for (d = data; len > 0; d += size, reg += size, len -= size) {
+		if (len >= 4) {
+			size = 4;
+#if defined(RTE_ARCH_X86)
+			*(uint32_t *)d = inl(reg);
+#else
+			*(uint32_t *)d = *(volatile uint32_t *)reg;
+#endif
+		} else if (len >= 2) {
+			size = 2;
+#if defined(RTE_ARCH_X86)
+			*(uint16_t *)d = inw(reg);
+#else
+			*(uint16_t *)d = *(volatile uint16_t *)reg;
+#endif
+		} else {
+			size = 1;
+#if defined(RTE_ARCH_X86)
+			*d = inb(reg);
+#else
+			*d = *(volatile uint8_t *)reg;
+#endif
+		}
+	}
+}
+
+void
+pci_uio_ioport_write(struct rte_pci_ioport *p,
+		     const void *data, size_t len, off_t offset)
+{
+	const uint8_t *s;
+	int size;
+	uintptr_t reg = p->base + offset;
+
+	for (s = data; len > 0; s += size, reg += size, len -= size) {
+		if (len >= 4) {
+			size = 4;
+#if defined(RTE_ARCH_X86)
+			outl_p(*(const uint32_t *)s, reg);
+#else
+			*(volatile uint32_t *)reg = *(const uint32_t *)s;
+#endif
+		} else if (len >= 2) {
+			size = 2;
+#if defined(RTE_ARCH_X86)
+			outw_p(*(const uint16_t *)s, reg);
+#else
+			*(volatile uint16_t *)reg = *(const uint16_t *)s;
+#endif
+		} else {
+			size = 1;
+#if defined(RTE_ARCH_X86)
+			outb_p(*s, reg);
+#else
+			*(volatile uint8_t *)reg = *s;
+#endif
+		}
+	}
+}
+
+int
+pci_uio_ioport_unmap(struct rte_pci_ioport *p)
+{
+#if defined(RTE_ARCH_X86)
+	RTE_SET_USED(p);
+	/* FIXME close intr fd ? */
+	return 0;
+#else
+	return munmap((void *)(uintptr_t)p->base, p->len);
+#endif
+}