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verilog syntax: clarify that also refers to systemverilog,

...and make sure it also takes .sv files as well.

Signed-off-by: Andrew Borodin <aborodin@vmail.ru>
Purdea Andrei 4 years ago
parent
commit
f32614ae7f
2 changed files with 3 additions and 2 deletions
  1. 1 1
      misc/syntax/Syntax.in
  2. 2 1
      misc/syntax/verilog.syntax

+ 1 - 1
misc/syntax/Syntax.in

@@ -235,7 +235,7 @@ include cabal.syntax
 file ..\*\\.(?i:n)$ Nemerle\sProgram
 include nemerle.syntax
 
-file ..\*\\.(?i:v)$ Verilog\sDevice\sDescription
+file ..\*\\.(?i:(v|sv))$ Verilog/SystemVerilog\sDevice\sDescription
 include verilog.syntax
 
 file ..\*\\.(?i:hdl|vhdl?)$ VHDL\sDevice\sDescription

+ 2 - 1
misc/syntax/verilog.syntax

@@ -1,5 +1,6 @@
-# This is Cooledit syntax-file for verilog
+# This is Cooledit syntax-file for Verilog and SystemVerilog
 # Created by Andres Farfan, <nafraf@linuxmail.org>
+# Updated by Andrei Purdea, <andrei@purdea.ro>
 # Feel free to copy & modify this.
 # 09/2004