cpu.c 6.8 KB

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  1. /*
  2. * CPU detection code, extracted from mmx.h
  3. * (c)1997-99 by H. Dietz and R. Fisher
  4. * Converted to C and improved by Fabrice Bellard.
  5. *
  6. * This file is part of FFmpeg.
  7. *
  8. * FFmpeg is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU Lesser General Public
  10. * License as published by the Free Software Foundation; either
  11. * version 2.1 of the License, or (at your option) any later version.
  12. *
  13. * FFmpeg is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * Lesser General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU Lesser General Public
  19. * License along with FFmpeg; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  21. */
  22. #include <stdlib.h>
  23. #include <string.h>
  24. #include "libavutil/x86/asm.h"
  25. #include "libavutil/x86/cpu.h"
  26. #include "libavutil/cpu.h"
  27. #if HAVE_YASM
  28. #define cpuid(index, eax, ebx, ecx, edx) \
  29. ff_cpu_cpuid(index, &eax, &ebx, &ecx, &edx)
  30. #define xgetbv(index, eax, edx) \
  31. ff_cpu_xgetbv(index, &eax, &edx)
  32. #elif HAVE_INLINE_ASM
  33. /* ebx saving is necessary for PIC. gcc seems unable to see it alone */
  34. #define cpuid(index, eax, ebx, ecx, edx) \
  35. __asm__ volatile ( \
  36. "mov %%"REG_b", %%"REG_S" \n\t" \
  37. "cpuid \n\t" \
  38. "xchg %%"REG_b", %%"REG_S \
  39. : "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \
  40. : "0" (index), "2"(0))
  41. #define xgetbv(index, eax, edx) \
  42. __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
  43. #define get_eflags(x) \
  44. __asm__ volatile ("pushfl \n" \
  45. "pop %0 \n" \
  46. : "=r"(x))
  47. #define set_eflags(x) \
  48. __asm__ volatile ("push %0 \n" \
  49. "popfl \n" \
  50. :: "r"(x))
  51. #endif /* HAVE_INLINE_ASM */
  52. #if ARCH_X86_64
  53. #define cpuid_test() 1
  54. #elif HAVE_YASM
  55. #define cpuid_test ff_cpu_cpuid_test
  56. #elif HAVE_INLINE_ASM
  57. static int cpuid_test(void)
  58. {
  59. x86_reg a, c;
  60. /* Check if CPUID is supported by attempting to toggle the ID bit in
  61. * the EFLAGS register. */
  62. get_eflags(a);
  63. set_eflags(a ^ 0x200000);
  64. get_eflags(c);
  65. return a != c;
  66. }
  67. #endif
  68. /* Function to test if multimedia instructions are supported... */
  69. int ff_get_cpu_flags_x86(void)
  70. {
  71. int rval = 0;
  72. #ifdef cpuid
  73. int eax, ebx, ecx, edx;
  74. int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0;
  75. int family = 0, model = 0;
  76. union { int i[3]; char c[12]; } vendor;
  77. if (!cpuid_test())
  78. return 0; /* CPUID not supported */
  79. cpuid(0, max_std_level, vendor.i[0], vendor.i[2], vendor.i[1]);
  80. if (max_std_level >= 1) {
  81. cpuid(1, eax, ebx, ecx, std_caps);
  82. family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
  83. model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0);
  84. if (std_caps & (1 << 15))
  85. rval |= AV_CPU_FLAG_CMOV;
  86. if (std_caps & (1 << 23))
  87. rval |= AV_CPU_FLAG_MMX;
  88. if (std_caps & (1 << 25))
  89. rval |= AV_CPU_FLAG_MMXEXT;
  90. #if HAVE_SSE
  91. if (std_caps & (1 << 25))
  92. rval |= AV_CPU_FLAG_SSE;
  93. if (std_caps & (1 << 26))
  94. rval |= AV_CPU_FLAG_SSE2;
  95. if (ecx & 1)
  96. rval |= AV_CPU_FLAG_SSE3;
  97. if (ecx & 0x00000200 )
  98. rval |= AV_CPU_FLAG_SSSE3;
  99. if (ecx & 0x00080000 )
  100. rval |= AV_CPU_FLAG_SSE4;
  101. if (ecx & 0x00100000 )
  102. rval |= AV_CPU_FLAG_SSE42;
  103. #if HAVE_AVX
  104. /* Check OXSAVE and AVX bits */
  105. if ((ecx & 0x18000000) == 0x18000000) {
  106. /* Check for OS support */
  107. xgetbv(0, eax, edx);
  108. if ((eax & 0x6) == 0x6)
  109. rval |= AV_CPU_FLAG_AVX;
  110. }
  111. #endif /* HAVE_AVX */
  112. #endif /* HAVE_SSE */
  113. }
  114. cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
  115. if (max_ext_level >= 0x80000001) {
  116. cpuid(0x80000001, eax, ebx, ecx, ext_caps);
  117. if (ext_caps & (1U << 31))
  118. rval |= AV_CPU_FLAG_3DNOW;
  119. if (ext_caps & (1 << 30))
  120. rval |= AV_CPU_FLAG_3DNOWEXT;
  121. if (ext_caps & (1 << 23))
  122. rval |= AV_CPU_FLAG_MMX;
  123. if (ext_caps & (1 << 22))
  124. rval |= AV_CPU_FLAG_MMXEXT;
  125. /* Allow for selectively disabling SSE2 functions on AMD processors
  126. with SSE2 support but not SSE4a. This includes Athlon64, some
  127. Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
  128. than SSE2 often enough to utilize this special-case flag.
  129. AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
  130. so that SSE2 is used unless explicitly disabled by checking
  131. AV_CPU_FLAG_SSE2SLOW. */
  132. if (!strncmp(vendor.c, "AuthenticAMD", 12) &&
  133. rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {
  134. rval |= AV_CPU_FLAG_SSE2SLOW;
  135. }
  136. /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
  137. * used unless the OS has AVX support. */
  138. if (rval & AV_CPU_FLAG_AVX) {
  139. if (ecx & 0x00000800)
  140. rval |= AV_CPU_FLAG_XOP;
  141. if (ecx & 0x00010000)
  142. rval |= AV_CPU_FLAG_FMA4;
  143. }
  144. }
  145. if (!strncmp(vendor.c, "GenuineIntel", 12)) {
  146. if (family == 6 && (model == 9 || model == 13 || model == 14)) {
  147. /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and
  148. * 6/14 (core1 "yonah") theoretically support sse2, but it's
  149. * usually slower than mmx, so let's just pretend they don't.
  150. * AV_CPU_FLAG_SSE2 is disabled and AV_CPU_FLAG_SSE2SLOW is
  151. * enabled so that SSE2 is not used unless explicitly enabled
  152. * by checking AV_CPU_FLAG_SSE2SLOW. The same situation
  153. * applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
  154. if (rval & AV_CPU_FLAG_SSE2)
  155. rval ^= AV_CPU_FLAG_SSE2SLOW | AV_CPU_FLAG_SSE2;
  156. if (rval & AV_CPU_FLAG_SSE3)
  157. rval ^= AV_CPU_FLAG_SSE3SLOW | AV_CPU_FLAG_SSE3;
  158. }
  159. /* The Atom processor has SSSE3 support, which is useful in many cases,
  160. * but sometimes the SSSE3 version is slower than the SSE2 equivalent
  161. * on the Atom, but is generally faster on other processors supporting
  162. * SSSE3. This flag allows for selectively disabling certain SSSE3
  163. * functions on the Atom. */
  164. if (family == 6 && model == 28)
  165. rval |= AV_CPU_FLAG_ATOM;
  166. }
  167. #endif /* cpuid */
  168. return rval;
  169. }