input.asm 39 KB

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  1. ;******************************************************************************
  2. ;* x86-optimized input routines; does shuffling of packed
  3. ;* YUV formats into individual planes, and converts RGB
  4. ;* into YUV planes also.
  5. ;* Copyright (c) 2012 Ronald S. Bultje <rsbultje@gmail.com>
  6. ;*
  7. ;* This file is part of FFmpeg.
  8. ;*
  9. ;* FFmpeg is free software; you can redistribute it and/or
  10. ;* modify it under the terms of the GNU Lesser General Public
  11. ;* License as published by the Free Software Foundation; either
  12. ;* version 2.1 of the License, or (at your option) any later version.
  13. ;*
  14. ;* FFmpeg is distributed in the hope that it will be useful,
  15. ;* but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. ;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. ;* Lesser General Public License for more details.
  18. ;*
  19. ;* You should have received a copy of the GNU Lesser General Public
  20. ;* License along with FFmpeg; if not, write to the Free Software
  21. ;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  22. ;******************************************************************************
  23. %include "libavutil/x86/x86util.asm"
  24. SECTION_RODATA
  25. %define RY 0x20DE
  26. %define GY 0x4087
  27. %define BY 0x0C88
  28. %define RU 0xECFF
  29. %define GU 0xDAC8
  30. %define BU 0x3838
  31. %define RV 0x3838
  32. %define GV 0xD0E3
  33. %define BV 0xF6E4
  34. rgb_Yrnd: times 4 dd 0x80100 ; 16.5 << 15
  35. rgb_UVrnd: times 4 dd 0x400100 ; 128.5 << 15
  36. %define bgr_Ycoeff_12x4 16*4 + 16* 0 + tableq
  37. %define bgr_Ycoeff_3x56 16*4 + 16* 1 + tableq
  38. %define rgb_Ycoeff_12x4 16*4 + 16* 2 + tableq
  39. %define rgb_Ycoeff_3x56 16*4 + 16* 3 + tableq
  40. %define bgr_Ucoeff_12x4 16*4 + 16* 4 + tableq
  41. %define bgr_Ucoeff_3x56 16*4 + 16* 5 + tableq
  42. %define rgb_Ucoeff_12x4 16*4 + 16* 6 + tableq
  43. %define rgb_Ucoeff_3x56 16*4 + 16* 7 + tableq
  44. %define bgr_Vcoeff_12x4 16*4 + 16* 8 + tableq
  45. %define bgr_Vcoeff_3x56 16*4 + 16* 9 + tableq
  46. %define rgb_Vcoeff_12x4 16*4 + 16*10 + tableq
  47. %define rgb_Vcoeff_3x56 16*4 + 16*11 + tableq
  48. %define rgba_Ycoeff_rb 16*4 + 16*12 + tableq
  49. %define rgba_Ycoeff_br 16*4 + 16*13 + tableq
  50. %define rgba_Ycoeff_ga 16*4 + 16*14 + tableq
  51. %define rgba_Ycoeff_ag 16*4 + 16*15 + tableq
  52. %define rgba_Ucoeff_rb 16*4 + 16*16 + tableq
  53. %define rgba_Ucoeff_br 16*4 + 16*17 + tableq
  54. %define rgba_Ucoeff_ga 16*4 + 16*18 + tableq
  55. %define rgba_Ucoeff_ag 16*4 + 16*19 + tableq
  56. %define rgba_Vcoeff_rb 16*4 + 16*20 + tableq
  57. %define rgba_Vcoeff_br 16*4 + 16*21 + tableq
  58. %define rgba_Vcoeff_ga 16*4 + 16*22 + tableq
  59. %define rgba_Vcoeff_ag 16*4 + 16*23 + tableq
  60. ; bgr_Ycoeff_12x4: times 2 dw BY, GY, 0, BY
  61. ; bgr_Ycoeff_3x56: times 2 dw RY, 0, GY, RY
  62. ; rgb_Ycoeff_12x4: times 2 dw RY, GY, 0, RY
  63. ; rgb_Ycoeff_3x56: times 2 dw BY, 0, GY, BY
  64. ; bgr_Ucoeff_12x4: times 2 dw BU, GU, 0, BU
  65. ; bgr_Ucoeff_3x56: times 2 dw RU, 0, GU, RU
  66. ; rgb_Ucoeff_12x4: times 2 dw RU, GU, 0, RU
  67. ; rgb_Ucoeff_3x56: times 2 dw BU, 0, GU, BU
  68. ; bgr_Vcoeff_12x4: times 2 dw BV, GV, 0, BV
  69. ; bgr_Vcoeff_3x56: times 2 dw RV, 0, GV, RV
  70. ; rgb_Vcoeff_12x4: times 2 dw RV, GV, 0, RV
  71. ; rgb_Vcoeff_3x56: times 2 dw BV, 0, GV, BV
  72. ; rgba_Ycoeff_rb: times 4 dw RY, BY
  73. ; rgba_Ycoeff_br: times 4 dw BY, RY
  74. ; rgba_Ycoeff_ga: times 4 dw GY, 0
  75. ; rgba_Ycoeff_ag: times 4 dw 0, GY
  76. ; rgba_Ucoeff_rb: times 4 dw RU, BU
  77. ; rgba_Ucoeff_br: times 4 dw BU, RU
  78. ; rgba_Ucoeff_ga: times 4 dw GU, 0
  79. ; rgba_Ucoeff_ag: times 4 dw 0, GU
  80. ; rgba_Vcoeff_rb: times 4 dw RV, BV
  81. ; rgba_Vcoeff_br: times 4 dw BV, RV
  82. ; rgba_Vcoeff_ga: times 4 dw GV, 0
  83. ; rgba_Vcoeff_ag: times 4 dw 0, GV
  84. shuf_rgb_12x4: db 0, 0x80, 1, 0x80, 2, 0x80, 3, 0x80, \
  85. 6, 0x80, 7, 0x80, 8, 0x80, 9, 0x80
  86. shuf_rgb_3x56: db 2, 0x80, 3, 0x80, 4, 0x80, 5, 0x80, \
  87. 8, 0x80, 9, 0x80, 10, 0x80, 11, 0x80
  88. pd_65535f: times 8 dd 65535.0
  89. pb_pack_shuffle16le: db 0, 1, 4, 5, \
  90. 8, 9, 12, 13, \
  91. -1, -1, -1, -1, \
  92. -1, -1, -1, -1, \
  93. -1, -1, -1, -1, \
  94. -1, -1, -1, -1, \
  95. 0, 1, 4, 5, \
  96. 8, 9, 12, 13
  97. pb_shuffle32be: db 3, 2, 1, 0, \
  98. 7, 6, 5, 4, \
  99. 11, 10, 9, 8, \
  100. 15, 14, 13, 12, \
  101. 3, 2, 1, 0, \
  102. 7, 6, 5, 4, \
  103. 11, 10, 9, 8, \
  104. 15, 14, 13, 12
  105. pb_shuffle16be: db 1, 0, 3, 2, \
  106. 5, 4, 7, 6, \
  107. 9, 8, 11, 10, \
  108. 13, 12, 15, 14, \
  109. 1, 0, 3, 2, \
  110. 5, 4, 7, 6, \
  111. 9, 8, 11, 10, \
  112. 13, 12, 15, 14
  113. SECTION .text
  114. ;-----------------------------------------------------------------------------
  115. ; RGB to Y/UV.
  116. ;
  117. ; void <fmt>ToY_<opt>(uint8_t *dst, const uint8_t *src, int w);
  118. ; and
  119. ; void <fmt>toUV_<opt>(uint8_t *dstU, uint8_t *dstV, const uint8_t *src,
  120. ; const uint8_t *unused, int w);
  121. ;-----------------------------------------------------------------------------
  122. ; %1 = nr. of XMM registers
  123. ; %2 = rgb or bgr
  124. %macro RGB24_TO_Y_FN 2-3
  125. cglobal %2 %+ 24ToY, 6, 6, %1, dst, src, u1, u2, w, table
  126. %if ARCH_X86_64
  127. mova m8, [%2_Ycoeff_12x4]
  128. mova m9, [%2_Ycoeff_3x56]
  129. %define coeff1 m8
  130. %define coeff2 m9
  131. %else ; x86-32
  132. %define coeff1 [%2_Ycoeff_12x4]
  133. %define coeff2 [%2_Ycoeff_3x56]
  134. %endif ; x86-32/64
  135. %if ARCH_X86_64 && %0 == 3
  136. jmp mangle(private_prefix %+ _ %+ %3 %+ 24ToY %+ SUFFIX).body
  137. %else ; ARCH_X86_64 && %0 == 3
  138. .body:
  139. %if cpuflag(ssse3)
  140. mova m7, [shuf_rgb_12x4]
  141. %define shuf_rgb1 m7
  142. %if ARCH_X86_64
  143. mova m10, [shuf_rgb_3x56]
  144. %define shuf_rgb2 m10
  145. %else ; x86-32
  146. %define shuf_rgb2 [shuf_rgb_3x56]
  147. %endif ; x86-32/64
  148. %endif ; cpuflag(ssse3)
  149. %if ARCH_X86_64
  150. movsxd wq, wd
  151. %endif
  152. add wq, wq
  153. add dstq, wq
  154. neg wq
  155. %if notcpuflag(ssse3)
  156. pxor m7, m7
  157. %endif ; !cpuflag(ssse3)
  158. mova m4, [rgb_Yrnd]
  159. .loop:
  160. %if cpuflag(ssse3)
  161. movu m0, [srcq+0] ; (byte) { Bx, Gx, Rx }[0-3]
  162. movu m2, [srcq+12] ; (byte) { Bx, Gx, Rx }[4-7]
  163. pshufb m1, m0, shuf_rgb2 ; (word) { R0, B1, G1, R1, R2, B3, G3, R3 }
  164. pshufb m0, shuf_rgb1 ; (word) { B0, G0, R0, B1, B2, G2, R2, B3 }
  165. pshufb m3, m2, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
  166. pshufb m2, shuf_rgb1 ; (word) { B4, G4, R4, B5, B6, G6, R6, B7 }
  167. %else ; !cpuflag(ssse3)
  168. movd m0, [srcq+0] ; (byte) { B0, G0, R0, B1 }
  169. movd m1, [srcq+2] ; (byte) { R0, B1, G1, R1 }
  170. movd m2, [srcq+6] ; (byte) { B2, G2, R2, B3 }
  171. movd m3, [srcq+8] ; (byte) { R2, B3, G3, R3 }
  172. punpckldq m0, m2 ; (byte) { B0, G0, R0, B1, B2, G2, R2, B3 }
  173. punpckldq m1, m3 ; (byte) { R0, B1, G1, R1, R2, B3, G3, R3 }
  174. movd m2, [srcq+12] ; (byte) { B4, G4, R4, B5 }
  175. movd m3, [srcq+14] ; (byte) { R4, B5, G5, R5 }
  176. movd m5, [srcq+18] ; (byte) { B6, G6, R6, B7 }
  177. movd m6, [srcq+20] ; (byte) { R6, B7, G7, R7 }
  178. punpckldq m2, m5 ; (byte) { B4, G4, R4, B5, B6, G6, R6, B7 }
  179. punpckldq m3, m6 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
  180. punpcklbw m0, m7 ; (word) { B0, G0, R0, B1, B2, G2, R2, B3 }
  181. punpcklbw m1, m7 ; (word) { R0, B1, G1, R1, R2, B3, G3, R3 }
  182. punpcklbw m2, m7 ; (word) { B4, G4, R4, B5, B6, G6, R6, B7 }
  183. punpcklbw m3, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
  184. %endif ; cpuflag(ssse3)
  185. add srcq, 3 * mmsize / 2
  186. pmaddwd m0, coeff1 ; (dword) { B0*BY + G0*GY, B1*BY, B2*BY + G2*GY, B3*BY }
  187. pmaddwd m1, coeff2 ; (dword) { R0*RY, G1+GY + R1*RY, R2*RY, G3+GY + R3*RY }
  188. pmaddwd m2, coeff1 ; (dword) { B4*BY + G4*GY, B5*BY, B6*BY + G6*GY, B7*BY }
  189. pmaddwd m3, coeff2 ; (dword) { R4*RY, G5+GY + R5*RY, R6*RY, G7+GY + R7*RY }
  190. paddd m0, m1 ; (dword) { Bx*BY + Gx*GY + Rx*RY }[0-3]
  191. paddd m2, m3 ; (dword) { Bx*BY + Gx*GY + Rx*RY }[4-7]
  192. paddd m0, m4 ; += rgb_Yrnd, i.e. (dword) { Y[0-3] }
  193. paddd m2, m4 ; += rgb_Yrnd, i.e. (dword) { Y[4-7] }
  194. psrad m0, 9
  195. psrad m2, 9
  196. packssdw m0, m2 ; (word) { Y[0-7] }
  197. mova [dstq+wq], m0
  198. add wq, mmsize
  199. jl .loop
  200. REP_RET
  201. %endif ; ARCH_X86_64 && %0 == 3
  202. %endmacro
  203. ; %1 = nr. of XMM registers
  204. ; %2 = rgb or bgr
  205. %macro RGB24_TO_UV_FN 2-3
  206. cglobal %2 %+ 24ToUV, 7, 7, %1, dstU, dstV, u1, src, u2, w, table
  207. %if ARCH_X86_64
  208. mova m8, [%2_Ucoeff_12x4]
  209. mova m9, [%2_Ucoeff_3x56]
  210. mova m10, [%2_Vcoeff_12x4]
  211. mova m11, [%2_Vcoeff_3x56]
  212. %define coeffU1 m8
  213. %define coeffU2 m9
  214. %define coeffV1 m10
  215. %define coeffV2 m11
  216. %else ; x86-32
  217. %define coeffU1 [%2_Ucoeff_12x4]
  218. %define coeffU2 [%2_Ucoeff_3x56]
  219. %define coeffV1 [%2_Vcoeff_12x4]
  220. %define coeffV2 [%2_Vcoeff_3x56]
  221. %endif ; x86-32/64
  222. %if ARCH_X86_64 && %0 == 3
  223. jmp mangle(private_prefix %+ _ %+ %3 %+ 24ToUV %+ SUFFIX).body
  224. %else ; ARCH_X86_64 && %0 == 3
  225. .body:
  226. %if cpuflag(ssse3)
  227. mova m7, [shuf_rgb_12x4]
  228. %define shuf_rgb1 m7
  229. %if ARCH_X86_64
  230. mova m12, [shuf_rgb_3x56]
  231. %define shuf_rgb2 m12
  232. %else ; x86-32
  233. %define shuf_rgb2 [shuf_rgb_3x56]
  234. %endif ; x86-32/64
  235. %endif ; cpuflag(ssse3)
  236. %if ARCH_X86_64
  237. movsxd wq, dword r5m
  238. %else ; x86-32
  239. mov wq, r5m
  240. %endif
  241. add wq, wq
  242. add dstUq, wq
  243. add dstVq, wq
  244. neg wq
  245. mova m6, [rgb_UVrnd]
  246. %if notcpuflag(ssse3)
  247. pxor m7, m7
  248. %endif
  249. .loop:
  250. %if cpuflag(ssse3)
  251. movu m0, [srcq+0] ; (byte) { Bx, Gx, Rx }[0-3]
  252. movu m4, [srcq+12] ; (byte) { Bx, Gx, Rx }[4-7]
  253. pshufb m1, m0, shuf_rgb2 ; (word) { R0, B1, G1, R1, R2, B3, G3, R3 }
  254. pshufb m0, shuf_rgb1 ; (word) { B0, G0, R0, B1, B2, G2, R2, B3 }
  255. %else ; !cpuflag(ssse3)
  256. movd m0, [srcq+0] ; (byte) { B0, G0, R0, B1 }
  257. movd m1, [srcq+2] ; (byte) { R0, B1, G1, R1 }
  258. movd m4, [srcq+6] ; (byte) { B2, G2, R2, B3 }
  259. movd m5, [srcq+8] ; (byte) { R2, B3, G3, R3 }
  260. punpckldq m0, m4 ; (byte) { B0, G0, R0, B1, B2, G2, R2, B3 }
  261. punpckldq m1, m5 ; (byte) { R0, B1, G1, R1, R2, B3, G3, R3 }
  262. movd m4, [srcq+12] ; (byte) { B4, G4, R4, B5 }
  263. movd m5, [srcq+14] ; (byte) { R4, B5, G5, R5 }
  264. punpcklbw m0, m7 ; (word) { B0, G0, R0, B1, B2, G2, R2, B3 }
  265. punpcklbw m1, m7 ; (word) { R0, B1, G1, R1, R2, B3, G3, R3 }
  266. %endif ; cpuflag(ssse3)
  267. pmaddwd m2, m0, coeffV1 ; (dword) { B0*BV + G0*GV, B1*BV, B2*BV + G2*GV, B3*BV }
  268. pmaddwd m3, m1, coeffV2 ; (dword) { R0*BV, G1*GV + R1*BV, R2*BV, G3*GV + R3*BV }
  269. pmaddwd m0, coeffU1 ; (dword) { B0*BU + G0*GU, B1*BU, B2*BU + G2*GU, B3*BU }
  270. pmaddwd m1, coeffU2 ; (dword) { R0*BU, G1*GU + R1*BU, R2*BU, G3*GU + R3*BU }
  271. paddd m0, m1 ; (dword) { Bx*BU + Gx*GU + Rx*RU }[0-3]
  272. paddd m2, m3 ; (dword) { Bx*BV + Gx*GV + Rx*RV }[0-3]
  273. %if cpuflag(ssse3)
  274. pshufb m5, m4, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
  275. pshufb m4, shuf_rgb1 ; (word) { B4, G4, R4, B5, B6, G6, R6, B7 }
  276. %else ; !cpuflag(ssse3)
  277. movd m1, [srcq+18] ; (byte) { B6, G6, R6, B7 }
  278. movd m3, [srcq+20] ; (byte) { R6, B7, G7, R7 }
  279. punpckldq m4, m1 ; (byte) { B4, G4, R4, B5, B6, G6, R6, B7 }
  280. punpckldq m5, m3 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
  281. punpcklbw m4, m7 ; (word) { B4, G4, R4, B5, B6, G6, R6, B7 }
  282. punpcklbw m5, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
  283. %endif ; cpuflag(ssse3)
  284. add srcq, 3 * mmsize / 2
  285. pmaddwd m1, m4, coeffU1 ; (dword) { B4*BU + G4*GU, B5*BU, B6*BU + G6*GU, B7*BU }
  286. pmaddwd m3, m5, coeffU2 ; (dword) { R4*BU, G5*GU + R5*BU, R6*BU, G7*GU + R7*BU }
  287. pmaddwd m4, coeffV1 ; (dword) { B4*BV + G4*GV, B5*BV, B6*BV + G6*GV, B7*BV }
  288. pmaddwd m5, coeffV2 ; (dword) { R4*BV, G5*GV + R5*BV, R6*BV, G7*GV + R7*BV }
  289. paddd m1, m3 ; (dword) { Bx*BU + Gx*GU + Rx*RU }[4-7]
  290. paddd m4, m5 ; (dword) { Bx*BV + Gx*GV + Rx*RV }[4-7]
  291. paddd m0, m6 ; += rgb_UVrnd, i.e. (dword) { U[0-3] }
  292. paddd m2, m6 ; += rgb_UVrnd, i.e. (dword) { V[0-3] }
  293. paddd m1, m6 ; += rgb_UVrnd, i.e. (dword) { U[4-7] }
  294. paddd m4, m6 ; += rgb_UVrnd, i.e. (dword) { V[4-7] }
  295. psrad m0, 9
  296. psrad m2, 9
  297. psrad m1, 9
  298. psrad m4, 9
  299. packssdw m0, m1 ; (word) { U[0-7] }
  300. packssdw m2, m4 ; (word) { V[0-7] }
  301. mova [dstUq+wq], m0
  302. mova [dstVq+wq], m2
  303. add wq, mmsize
  304. jl .loop
  305. REP_RET
  306. %endif ; ARCH_X86_64 && %0 == 3
  307. %endmacro
  308. ; %1 = nr. of XMM registers for rgb-to-Y func
  309. ; %2 = nr. of XMM registers for rgb-to-UV func
  310. %macro RGB24_FUNCS 2
  311. RGB24_TO_Y_FN %1, rgb
  312. RGB24_TO_Y_FN %1, bgr, rgb
  313. RGB24_TO_UV_FN %2, rgb
  314. RGB24_TO_UV_FN %2, bgr, rgb
  315. %endmacro
  316. INIT_XMM sse2
  317. RGB24_FUNCS 10, 12
  318. INIT_XMM ssse3
  319. RGB24_FUNCS 11, 13
  320. %if HAVE_AVX_EXTERNAL
  321. INIT_XMM avx
  322. RGB24_FUNCS 11, 13
  323. %endif
  324. ; %1 = nr. of XMM registers
  325. ; %2-5 = rgba, bgra, argb or abgr (in individual characters)
  326. %macro RGB32_TO_Y_FN 5-6
  327. cglobal %2%3%4%5 %+ ToY, 6, 6, %1, dst, src, u1, u2, w, table
  328. mova m5, [rgba_Ycoeff_%2%4]
  329. mova m6, [rgba_Ycoeff_%3%5]
  330. %if %0 == 6
  331. jmp mangle(private_prefix %+ _ %+ %6 %+ ToY %+ SUFFIX).body
  332. %else ; %0 == 6
  333. .body:
  334. %if ARCH_X86_64
  335. movsxd wq, wd
  336. %endif
  337. add wq, wq
  338. sub wq, mmsize - 1
  339. lea srcq, [srcq+wq*2]
  340. add dstq, wq
  341. neg wq
  342. mova m4, [rgb_Yrnd]
  343. pcmpeqb m7, m7
  344. psrlw m7, 8 ; (word) { 0x00ff } x4
  345. .loop:
  346. ; FIXME check alignment and use mova
  347. movu m0, [srcq+wq*2+0] ; (byte) { Bx, Gx, Rx, xx }[0-3]
  348. movu m2, [srcq+wq*2+mmsize] ; (byte) { Bx, Gx, Rx, xx }[4-7]
  349. DEINTB 1, 0, 3, 2, 7 ; (word) { Gx, xx (m0/m2) or Bx, Rx (m1/m3) }[0-3]/[4-7]
  350. pmaddwd m1, m5 ; (dword) { Bx*BY + Rx*RY }[0-3]
  351. pmaddwd m0, m6 ; (dword) { Gx*GY }[0-3]
  352. pmaddwd m3, m5 ; (dword) { Bx*BY + Rx*RY }[4-7]
  353. pmaddwd m2, m6 ; (dword) { Gx*GY }[4-7]
  354. paddd m0, m4 ; += rgb_Yrnd
  355. paddd m2, m4 ; += rgb_Yrnd
  356. paddd m0, m1 ; (dword) { Y[0-3] }
  357. paddd m2, m3 ; (dword) { Y[4-7] }
  358. psrad m0, 9
  359. psrad m2, 9
  360. packssdw m0, m2 ; (word) { Y[0-7] }
  361. mova [dstq+wq], m0
  362. add wq, mmsize
  363. jl .loop
  364. sub wq, mmsize - 1
  365. jz .end
  366. add srcq, 2*mmsize - 2
  367. add dstq, mmsize - 1
  368. .loop2:
  369. movd m0, [srcq+wq*2+0] ; (byte) { Bx, Gx, Rx, xx }[0-3]
  370. DEINTB 1, 0, 3, 2, 7 ; (word) { Gx, xx (m0/m2) or Bx, Rx (m1/m3) }[0-3]/[4-7]
  371. pmaddwd m1, m5 ; (dword) { Bx*BY + Rx*RY }[0-3]
  372. pmaddwd m0, m6 ; (dword) { Gx*GY }[0-3]
  373. paddd m0, m4 ; += rgb_Yrnd
  374. paddd m0, m1 ; (dword) { Y[0-3] }
  375. psrad m0, 9
  376. packssdw m0, m0 ; (word) { Y[0-7] }
  377. movd [dstq+wq], m0
  378. add wq, 2
  379. jl .loop2
  380. .end:
  381. REP_RET
  382. %endif ; %0 == 3
  383. %endmacro
  384. ; %1 = nr. of XMM registers
  385. ; %2-5 = rgba, bgra, argb or abgr (in individual characters)
  386. %macro RGB32_TO_UV_FN 5-6
  387. cglobal %2%3%4%5 %+ ToUV, 7, 7, %1, dstU, dstV, u1, src, u2, w, table
  388. %if ARCH_X86_64
  389. mova m8, [rgba_Ucoeff_%2%4]
  390. mova m9, [rgba_Ucoeff_%3%5]
  391. mova m10, [rgba_Vcoeff_%2%4]
  392. mova m11, [rgba_Vcoeff_%3%5]
  393. %define coeffU1 m8
  394. %define coeffU2 m9
  395. %define coeffV1 m10
  396. %define coeffV2 m11
  397. %else ; x86-32
  398. %define coeffU1 [rgba_Ucoeff_%2%4]
  399. %define coeffU2 [rgba_Ucoeff_%3%5]
  400. %define coeffV1 [rgba_Vcoeff_%2%4]
  401. %define coeffV2 [rgba_Vcoeff_%3%5]
  402. %endif ; x86-64/32
  403. %if ARCH_X86_64 && %0 == 6
  404. jmp mangle(private_prefix %+ _ %+ %6 %+ ToUV %+ SUFFIX).body
  405. %else ; ARCH_X86_64 && %0 == 6
  406. .body:
  407. %if ARCH_X86_64
  408. movsxd wq, dword r5m
  409. %else ; x86-32
  410. mov wq, r5m
  411. %endif
  412. add wq, wq
  413. sub wq, mmsize - 1
  414. add dstUq, wq
  415. add dstVq, wq
  416. lea srcq, [srcq+wq*2]
  417. neg wq
  418. pcmpeqb m7, m7
  419. psrlw m7, 8 ; (word) { 0x00ff } x4
  420. mova m6, [rgb_UVrnd]
  421. .loop:
  422. ; FIXME check alignment and use mova
  423. movu m0, [srcq+wq*2+0] ; (byte) { Bx, Gx, Rx, xx }[0-3]
  424. movu m4, [srcq+wq*2+mmsize] ; (byte) { Bx, Gx, Rx, xx }[4-7]
  425. DEINTB 1, 0, 5, 4, 7 ; (word) { Gx, xx (m0/m4) or Bx, Rx (m1/m5) }[0-3]/[4-7]
  426. pmaddwd m3, m1, coeffV1 ; (dword) { Bx*BV + Rx*RV }[0-3]
  427. pmaddwd m2, m0, coeffV2 ; (dword) { Gx*GV }[0-3]
  428. pmaddwd m1, coeffU1 ; (dword) { Bx*BU + Rx*RU }[0-3]
  429. pmaddwd m0, coeffU2 ; (dword) { Gx*GU }[0-3]
  430. paddd m3, m6 ; += rgb_UVrnd
  431. paddd m1, m6 ; += rgb_UVrnd
  432. paddd m2, m3 ; (dword) { V[0-3] }
  433. paddd m0, m1 ; (dword) { U[0-3] }
  434. pmaddwd m3, m5, coeffV1 ; (dword) { Bx*BV + Rx*RV }[4-7]
  435. pmaddwd m1, m4, coeffV2 ; (dword) { Gx*GV }[4-7]
  436. pmaddwd m5, coeffU1 ; (dword) { Bx*BU + Rx*RU }[4-7]
  437. pmaddwd m4, coeffU2 ; (dword) { Gx*GU }[4-7]
  438. paddd m3, m6 ; += rgb_UVrnd
  439. paddd m5, m6 ; += rgb_UVrnd
  440. psrad m0, 9
  441. paddd m1, m3 ; (dword) { V[4-7] }
  442. paddd m4, m5 ; (dword) { U[4-7] }
  443. psrad m2, 9
  444. psrad m4, 9
  445. psrad m1, 9
  446. packssdw m0, m4 ; (word) { U[0-7] }
  447. packssdw m2, m1 ; (word) { V[0-7] }
  448. mova [dstUq+wq], m0
  449. mova [dstVq+wq], m2
  450. add wq, mmsize
  451. jl .loop
  452. sub wq, mmsize - 1
  453. jz .end
  454. add srcq , 2*mmsize - 2
  455. add dstUq, mmsize - 1
  456. add dstVq, mmsize - 1
  457. .loop2:
  458. movd m0, [srcq+wq*2] ; (byte) { Bx, Gx, Rx, xx }[0-3]
  459. DEINTB 1, 0, 5, 4, 7 ; (word) { Gx, xx (m0/m4) or Bx, Rx (m1/m5) }[0-3]/[4-7]
  460. pmaddwd m3, m1, coeffV1 ; (dword) { Bx*BV + Rx*RV }[0-3]
  461. pmaddwd m2, m0, coeffV2 ; (dword) { Gx*GV }[0-3]
  462. pmaddwd m1, coeffU1 ; (dword) { Bx*BU + Rx*RU }[0-3]
  463. pmaddwd m0, coeffU2 ; (dword) { Gx*GU }[0-3]
  464. paddd m3, m6 ; += rgb_UVrnd
  465. paddd m1, m6 ; += rgb_UVrnd
  466. paddd m2, m3 ; (dword) { V[0-3] }
  467. paddd m0, m1 ; (dword) { U[0-3] }
  468. psrad m0, 9
  469. psrad m2, 9
  470. packssdw m0, m0 ; (word) { U[0-7] }
  471. packssdw m2, m2 ; (word) { V[0-7] }
  472. movd [dstUq+wq], m0
  473. movd [dstVq+wq], m2
  474. add wq, 2
  475. jl .loop2
  476. .end:
  477. REP_RET
  478. %endif ; ARCH_X86_64 && %0 == 3
  479. %endmacro
  480. ; %1 = nr. of XMM registers for rgb-to-Y func
  481. ; %2 = nr. of XMM registers for rgb-to-UV func
  482. %macro RGB32_FUNCS 2
  483. RGB32_TO_Y_FN %1, r, g, b, a
  484. RGB32_TO_Y_FN %1, b, g, r, a, rgba
  485. RGB32_TO_Y_FN %1, a, r, g, b, rgba
  486. RGB32_TO_Y_FN %1, a, b, g, r, rgba
  487. RGB32_TO_UV_FN %2, r, g, b, a
  488. RGB32_TO_UV_FN %2, b, g, r, a, rgba
  489. RGB32_TO_UV_FN %2, a, r, g, b, rgba
  490. RGB32_TO_UV_FN %2, a, b, g, r, rgba
  491. %endmacro
  492. INIT_XMM sse2
  493. RGB32_FUNCS 8, 12
  494. %if HAVE_AVX_EXTERNAL
  495. INIT_XMM avx
  496. RGB32_FUNCS 8, 12
  497. %endif
  498. ;-----------------------------------------------------------------------------
  499. ; YUYV/UYVY/NV12/NV21 packed pixel shuffling.
  500. ;
  501. ; void <fmt>ToY_<opt>(uint8_t *dst, const uint8_t *src, int w);
  502. ; and
  503. ; void <fmt>toUV_<opt>(uint8_t *dstU, uint8_t *dstV, const uint8_t *src,
  504. ; const uint8_t *unused, int w);
  505. ;-----------------------------------------------------------------------------
  506. ; %1 = a (aligned) or u (unaligned)
  507. ; %2 = yuyv or uyvy
  508. %macro LOOP_YUYV_TO_Y 2
  509. .loop_%1:
  510. mov%1 m0, [srcq+wq*2] ; (byte) { Y0, U0, Y1, V0, ... }
  511. mov%1 m1, [srcq+wq*2+mmsize] ; (byte) { Y8, U4, Y9, V4, ... }
  512. %ifidn %2, yuyv
  513. pand m0, m2 ; (word) { Y0, Y1, ..., Y7 }
  514. pand m1, m2 ; (word) { Y8, Y9, ..., Y15 }
  515. %else ; uyvy
  516. psrlw m0, 8 ; (word) { Y0, Y1, ..., Y7 }
  517. psrlw m1, 8 ; (word) { Y8, Y9, ..., Y15 }
  518. %endif ; yuyv/uyvy
  519. packuswb m0, m1 ; (byte) { Y0, ..., Y15 }
  520. mova [dstq+wq], m0
  521. add wq, mmsize
  522. jl .loop_%1
  523. REP_RET
  524. %endmacro
  525. ; %1 = nr. of XMM registers
  526. ; %2 = yuyv or uyvy
  527. ; %3 = if specified, it means that unaligned and aligned code in loop
  528. ; will be the same (i.e. YUYV+AVX), and thus we don't need to
  529. ; split the loop in an aligned and unaligned case
  530. %macro YUYV_TO_Y_FN 2-3
  531. cglobal %2ToY, 5, 5, %1, dst, unused0, unused1, src, w
  532. %if ARCH_X86_64
  533. movsxd wq, wd
  534. %endif
  535. add dstq, wq
  536. test srcq, 15
  537. lea srcq, [srcq+wq*2]
  538. %ifidn %2, yuyv
  539. pcmpeqb m2, m2 ; (byte) { 0xff } x 16
  540. psrlw m2, 8 ; (word) { 0x00ff } x 8
  541. %endif ; yuyv
  542. jnz .loop_u_start
  543. neg wq
  544. LOOP_YUYV_TO_Y a, %2
  545. .loop_u_start:
  546. neg wq
  547. LOOP_YUYV_TO_Y u, %2
  548. %endmacro
  549. ; %1 = a (aligned) or u (unaligned)
  550. ; %2 = yuyv or uyvy
  551. %macro LOOP_YUYV_TO_UV 2
  552. .loop_%1:
  553. %ifidn %2, yuyv
  554. mov%1 m0, [srcq+wq*4] ; (byte) { Y0, U0, Y1, V0, ... }
  555. mov%1 m1, [srcq+wq*4+mmsize] ; (byte) { Y8, U4, Y9, V4, ... }
  556. psrlw m0, 8 ; (word) { U0, V0, ..., U3, V3 }
  557. psrlw m1, 8 ; (word) { U4, V4, ..., U7, V7 }
  558. %else ; uyvy
  559. %if cpuflag(avx)
  560. vpand m0, m2, [srcq+wq*4] ; (word) { U0, V0, ..., U3, V3 }
  561. vpand m1, m2, [srcq+wq*4+mmsize] ; (word) { U4, V4, ..., U7, V7 }
  562. %else
  563. mov%1 m0, [srcq+wq*4] ; (byte) { Y0, U0, Y1, V0, ... }
  564. mov%1 m1, [srcq+wq*4+mmsize] ; (byte) { Y8, U4, Y9, V4, ... }
  565. pand m0, m2 ; (word) { U0, V0, ..., U3, V3 }
  566. pand m1, m2 ; (word) { U4, V4, ..., U7, V7 }
  567. %endif
  568. %endif ; yuyv/uyvy
  569. packuswb m0, m1 ; (byte) { U0, V0, ..., U7, V7 }
  570. pand m1, m0, m2 ; (word) { U0, U1, ..., U7 }
  571. psrlw m0, 8 ; (word) { V0, V1, ..., V7 }
  572. packuswb m1, m0 ; (byte) { U0, ... U7, V1, ... V7 }
  573. movh [dstUq+wq], m1
  574. movhps [dstVq+wq], m1
  575. add wq, mmsize / 2
  576. jl .loop_%1
  577. REP_RET
  578. %endmacro
  579. ; %1 = nr. of XMM registers
  580. ; %2 = yuyv or uyvy
  581. ; %3 = if specified, it means that unaligned and aligned code in loop
  582. ; will be the same (i.e. UYVY+AVX), and thus we don't need to
  583. ; split the loop in an aligned and unaligned case
  584. %macro YUYV_TO_UV_FN 2-3
  585. cglobal %2ToUV, 4, 5, %1, dstU, dstV, unused, src, w
  586. %if ARCH_X86_64
  587. movsxd wq, dword r5m
  588. %else ; x86-32
  589. mov wq, r5m
  590. %endif
  591. add dstUq, wq
  592. add dstVq, wq
  593. %if %0 == 2
  594. test srcq, 15
  595. %endif
  596. lea srcq, [srcq+wq*4]
  597. pcmpeqb m2, m2 ; (byte) { 0xff } x 16
  598. psrlw m2, 8 ; (word) { 0x00ff } x 8
  599. ; NOTE: if uyvy+avx, u/a are identical
  600. %if %0 == 2
  601. jnz .loop_u_start
  602. neg wq
  603. LOOP_YUYV_TO_UV a, %2
  604. .loop_u_start:
  605. neg wq
  606. LOOP_YUYV_TO_UV u, %2
  607. %else
  608. neg wq
  609. LOOP_YUYV_TO_UV a, %2
  610. %endif
  611. %endmacro
  612. ; %1 = a (aligned) or u (unaligned)
  613. ; %2 = nv12 or nv21
  614. %macro LOOP_NVXX_TO_UV 2
  615. .loop_%1:
  616. mov%1 m0, [srcq+wq*2] ; (byte) { U0, V0, U1, V1, ... }
  617. mov%1 m1, [srcq+wq*2+mmsize] ; (byte) { U8, V8, U9, V9, ... }
  618. pand m2, m0, m5 ; (word) { U0, U1, ..., U7 }
  619. pand m3, m1, m5 ; (word) { U8, U9, ..., U15 }
  620. psrlw m0, 8 ; (word) { V0, V1, ..., V7 }
  621. psrlw m1, 8 ; (word) { V8, V9, ..., V15 }
  622. packuswb m2, m3 ; (byte) { U0, ..., U15 }
  623. packuswb m0, m1 ; (byte) { V0, ..., V15 }
  624. %ifidn %2, nv12
  625. mova [dstUq+wq], m2
  626. mova [dstVq+wq], m0
  627. %else ; nv21
  628. mova [dstVq+wq], m2
  629. mova [dstUq+wq], m0
  630. %endif ; nv12/21
  631. add wq, mmsize
  632. jl .loop_%1
  633. REP_RET
  634. %endmacro
  635. ; %1 = nr. of XMM registers
  636. ; %2 = nv12 or nv21
  637. %macro NVXX_TO_UV_FN 2
  638. cglobal %2ToUV, 4, 5, %1, dstU, dstV, unused, src, w
  639. %if ARCH_X86_64
  640. movsxd wq, dword r5m
  641. %else ; x86-32
  642. mov wq, r5m
  643. %endif
  644. add dstUq, wq
  645. add dstVq, wq
  646. test srcq, 15
  647. lea srcq, [srcq+wq*2]
  648. pcmpeqb m5, m5 ; (byte) { 0xff } x 16
  649. psrlw m5, 8 ; (word) { 0x00ff } x 8
  650. jnz .loop_u_start
  651. neg wq
  652. LOOP_NVXX_TO_UV a, %2
  653. .loop_u_start:
  654. neg wq
  655. LOOP_NVXX_TO_UV u, %2
  656. %endmacro
  657. INIT_XMM sse2
  658. YUYV_TO_Y_FN 3, yuyv
  659. YUYV_TO_Y_FN 2, uyvy
  660. YUYV_TO_UV_FN 3, yuyv
  661. YUYV_TO_UV_FN 3, uyvy
  662. NVXX_TO_UV_FN 5, nv12
  663. NVXX_TO_UV_FN 5, nv21
  664. %if HAVE_AVX_EXTERNAL
  665. INIT_XMM avx
  666. ; in theory, we could write a yuy2-to-y using vpand (i.e. AVX), but
  667. ; that's not faster in practice
  668. YUYV_TO_UV_FN 3, yuyv
  669. YUYV_TO_UV_FN 3, uyvy, 1
  670. NVXX_TO_UV_FN 5, nv12
  671. NVXX_TO_UV_FN 5, nv21
  672. %endif
  673. %if ARCH_X86_64
  674. %define RY_IDX 0
  675. %define GY_IDX 1
  676. %define BY_IDX 2
  677. %define RU_IDX 3
  678. %define GU_IDX 4
  679. %define BU_IDX 5
  680. %define RV_IDX 6
  681. %define GV_IDX 7
  682. %define BV_IDX 8
  683. %define RGB2YUV_SHIFT 15
  684. %define R m0
  685. %define G m1
  686. %define B m2
  687. %macro SWAP32 1
  688. %if mmsize > 16 || cpuflag(sse4)
  689. pshufb m%1, [pb_shuffle32be]
  690. %else
  691. psrlw xm7, xm%1, 8
  692. psllw xm%1, 8
  693. por xm%1, xm7
  694. pshuflw xm%1, xm%1, (2 << 6 | 3 << 4 | 0 << 2 | 1 << 0)
  695. pshufhw xm%1, xm%1, (2 << 6 | 3 << 4 | 0 << 2 | 1 << 0)
  696. %endif
  697. %endmacro
  698. ; 1 - dest
  699. ; 2 - source
  700. ; 3 - is big endian
  701. ; 4 - load only 2 values on sse2
  702. %macro LOADF32 4
  703. %if notcpuflag(sse4) && %4
  704. %if %3 ; big endian
  705. mov tmp1q, %2
  706. bswap tmp1q
  707. movq xm%1, tmp1q
  708. %else
  709. movq m%1, %2
  710. %endif
  711. %else
  712. movu m%1, %2
  713. %if %3
  714. SWAP32 %1
  715. %endif
  716. %endif
  717. maxps m%1, m9 ; 0.0 (nan, -inf) -> 0.0
  718. mulps m%1, m8 ; [pd_65535f]
  719. minps m%1, m8 ; +inf -> 65535
  720. ; cvtps2dq rounds to nearest int
  721. ; assuming mxcsr register is default rounding
  722. ; 0.40 -> 0.0, 0.50 -> 0.0, 0.51 -> 1.0
  723. cvtps2dq m%1, m%1
  724. %if notcpuflag(sse4) && %4
  725. ; line up the 2 values in lanes 0,2
  726. %if %3 ; big endian
  727. pshufd m%1, m%1, (3 << 6 | 0 << 4 | 2 << 2 | 1 << 0)
  728. %else
  729. pshufd m%1, m%1, (3 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  730. %endif
  731. %endif
  732. %endmacro
  733. ; 1 - dest
  734. ; 2 - source
  735. ; 3 - is big endian
  736. %macro LOAD16 3
  737. %if cpuflag(sse4) || mmsize > 16
  738. pmovzxwd m%1, %2
  739. %if %3 ; bigendian
  740. pshufb m%1, m8 ; [pb_shuffle16be]
  741. %endif
  742. %else
  743. %if %3 ; bigendian
  744. mov tmp1d, dword %2
  745. bswap tmp1d
  746. movd xm%1, tmp1d
  747. pshuflw m%1, m%1, (3 << 6 | 0 << 4 | 3 << 2 | 1 << 0)
  748. pshufd m%1, m%1, (3 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  749. %else
  750. movd xm%1, %2
  751. punpcklwd m%1, m9 ; interleave words with zero
  752. pshufd m%1, m%1, (3 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  753. %endif
  754. %endif
  755. %endmacro
  756. %macro LOAD8_RGB 0
  757. %if cpuflag(sse4) || mmsize > 16
  758. pmovzxbd R, [srcRq + xq]
  759. pmovzxbd G, [srcGq + xq]
  760. pmovzxbd B, [srcBq + xq]
  761. %else
  762. ; thought this would be faster but from my measurments its not
  763. ; movd m0, [srcRq + xq + 0]; overeads by 2 bytes
  764. ; punpcklbw m0, m9 ; interleave bytes with zero
  765. ; punpcklwd m0, m9 ; interleave words with zero
  766. ; pshufd m0, m0, (3 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  767. movzx tmp2q, byte [srcRq + xq + 1]
  768. movzx tmp1q, byte [srcRq + xq + 0]
  769. shl tmp2q, 32
  770. or tmp1q, tmp2q
  771. movq xm0, tmp1q
  772. movzx tmp2q, byte [srcGq + xq + 1]
  773. movzx tmp3q, byte [srcGq + xq + 0]
  774. shl tmp2q, 32
  775. or tmp3q, tmp2q
  776. movq xm1, tmp3q
  777. movzx tmp2q, byte [srcBq + xq + 1]
  778. movzx tmp1q, byte [srcBq + xq + 0]
  779. shl tmp2q, 32
  780. or tmp1q, tmp2q
  781. movq xm2, tmp1q
  782. pshufd m0, m0, (3 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  783. pshufd m1, m1, (3 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  784. pshufd m2, m2, (3 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  785. %endif
  786. %endmacro
  787. ; 1 - dest
  788. ; 2 - source
  789. ; 3 - store only 2 values on sse2
  790. %macro STORE16 3
  791. %if %3 && notcpuflag(sse4)
  792. pshufd m%2, m%2, (3 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  793. pshuflw m%2, m%2, (3 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  794. movd %1, m%2
  795. %elif mmsize > 16
  796. pshufb m%2, m7 ; [pb_pack_shuffle16le]
  797. vpermq m%2, m%2, (3 << 6 | 0 << 4 | 3 << 2 | 0 << 0)
  798. movu %1, xm%2
  799. %else
  800. %if cpuflag(sse4)
  801. pshufb m%2, m7 ; [pb_pack_shuffle16le]
  802. %else
  803. pshuflw m%2, m%2, (1 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  804. pshufhw m%2, m%2, (1 << 6 | 1 << 4 | 2 << 2 | 0 << 0)
  805. pshufd m%2, m%2, (3 << 6 | 3 << 4 | 2 << 2 | 0 << 0)
  806. %endif
  807. movq %1, m%2
  808. %endif
  809. %endmacro
  810. %macro PMUL 3
  811. %if cpuflag(sse4) || mmsize > 16
  812. pmulld %1, %2, %3
  813. %else
  814. pmuludq %1, %2, %3
  815. %endif
  816. %endmacro
  817. ; 1 - name
  818. ; 2 - depth
  819. ; 3 - is big endian
  820. ; 4 - is float
  821. ; in sse2 mode only 2 values are done per loop, due to lack of pmulld instruction
  822. %macro planar_rgb_to_y_fn 4
  823. %if %2 == 8
  824. %define OFFSET (0x801<<(RGB2YUV_SHIFT-7))
  825. %define RSHIFT (RGB2YUV_SHIFT-6)
  826. %else
  827. %if %2 < 16
  828. %define SHIFT %2
  829. %define BPC %2
  830. %else
  831. %define SHIFT 14
  832. %define BPC 16
  833. %endif
  834. %define OFFSET ((16 << (RGB2YUV_SHIFT + BPC - 8)) + (1 << (RGB2YUV_SHIFT + SHIFT - 15)))
  835. %define RSHIFT (RGB2YUV_SHIFT + SHIFT - 14)
  836. %endif
  837. cglobal planar_%1_to_y, 4, 12, 13, dst, src, w, rgb2yuv, srcR, srcG, srcB, x, tmp1, tmp2, tmp3, tmp4
  838. VBROADCASTSS m10, dword [rgb2yuvq + RY_IDX*4] ; ry
  839. VBROADCASTSS m11, dword [rgb2yuvq + GY_IDX*4] ; gy
  840. VBROADCASTSS m12, dword [rgb2yuvq + BY_IDX*4] ; by
  841. pxor m9, m9
  842. %if %4
  843. movu m8, [pd_65535f]
  844. %endif
  845. %if cpuflag(sse4) || mmsize > 16
  846. movu m7, [pb_pack_shuffle16le]
  847. %if %3 && %2 > 8 && %2 <= 16
  848. movu m8, [pb_shuffle16be]
  849. %endif
  850. %endif
  851. mov xq, OFFSET
  852. movq xm6, xq
  853. VBROADCASTSS m6, xm6
  854. mov srcGq, [srcq + 0]
  855. mov srcBq, [srcq + 8]
  856. mov srcRq, [srcq + 16]
  857. xor xq, xq
  858. %%loop_x:
  859. %if %4
  860. LOADF32 0, [srcRq + xq*4], %3, 1
  861. LOADF32 1, [srcGq + xq*4], %3, 1
  862. LOADF32 2, [srcBq + xq*4], %3, 1
  863. %elif %2 == 8
  864. LOAD8_RGB
  865. %else
  866. LOAD16 0, [srcRq + xq*2], %3
  867. LOAD16 1, [srcGq + xq*2], %3
  868. LOAD16 2, [srcBq + xq*2], %3
  869. %endif
  870. PMUL R, R, m10 ; r*ry
  871. PMUL G, G, m11 ; g*gy
  872. PMUL B, B, m12 ; b*by
  873. paddd m0, m6 ; + OFFSET
  874. paddd B, G
  875. paddd m0, B
  876. psrad m0, RSHIFT
  877. STORE16 [dstq + 2*xq], 0, 1
  878. %if cpuflag(avx2) || cpuflag(sse4)
  879. add xq, mmsize/4
  880. %else
  881. add xd, 2
  882. %endif
  883. cmp xd, wd
  884. jl %%loop_x
  885. RET
  886. %endmacro
  887. ; 1 - name
  888. ; 2 - depth
  889. ; 3 - is big endian
  890. ; 4 - is float
  891. ; in sse2 mode only 2 values are done per loop, due to lack of pmulld instruction
  892. %macro planar_rgb_to_uv_fn 4
  893. %if %2 == 8
  894. %define OFFSET (0x4001<<(RGB2YUV_SHIFT-7))
  895. %define RSHIFT (RGB2YUV_SHIFT-6)
  896. %else
  897. %if %2 < 16
  898. %define SHIFT %2
  899. %define BPC %2
  900. %else
  901. %define SHIFT 14
  902. %define BPC 16
  903. %endif
  904. %define OFFSET ((128 << (RGB2YUV_SHIFT + BPC - 8)) + (1 << (RGB2YUV_SHIFT + SHIFT - 15)))
  905. %define RSHIFT (RGB2YUV_SHIFT + SHIFT - 14)
  906. %endif
  907. cglobal planar_%1_to_uv, 5, 12, 16, dstU, dstV, src, w, rgb2yuv, srcR, srcG, srcB, x, tmp1, tmp2, tmp3
  908. VBROADCASTSS m10, dword [rgb2yuvq + RU_IDX*4] ; ru
  909. VBROADCASTSS m11, dword [rgb2yuvq + GU_IDX*4] ; gu
  910. VBROADCASTSS m12, dword [rgb2yuvq + BU_IDX*4] ; bu
  911. VBROADCASTSS m13, dword [rgb2yuvq + RV_IDX*4] ; rv
  912. VBROADCASTSS m14, dword [rgb2yuvq + GV_IDX*4] ; gv
  913. VBROADCASTSS m15, dword [rgb2yuvq + BV_IDX*4] ; bv
  914. pxor m9, m9
  915. %if %4
  916. movu m8, [pd_65535f]
  917. %endif
  918. %if cpuflag(sse4) || mmsize > 16
  919. movu m7, [pb_pack_shuffle16le]
  920. %if %3 && %2 > 8 && %2 <= 16
  921. movu m8, [pb_shuffle16be]
  922. %endif
  923. %endif
  924. mov xq, OFFSET
  925. movq xm6, xq
  926. VBROADCASTSS m6, xm6
  927. mov srcGq, [srcq + 0]
  928. mov srcBq, [srcq + 8]
  929. mov srcRq, [srcq + 16]
  930. xor xq, xq
  931. %%loop_x:
  932. %if %4
  933. LOADF32 0, [srcRq + xq*4], %3, 1
  934. LOADF32 1, [srcGq + xq*4], %3, 1
  935. LOADF32 2, [srcBq + xq*4], %3, 1
  936. %elif %2 == 8
  937. LOAD8_RGB
  938. %else
  939. LOAD16 0, [srcRq + xq*2], %3
  940. LOAD16 1, [srcGq + xq*2], %3
  941. LOAD16 2, [srcBq + xq*2], %3
  942. %endif
  943. PMUL m5, R, m10 ; r*ru
  944. PMUL m4, G, m11 ; b*gu
  945. paddd m4, m5
  946. PMUL m5, B, m12 ; b*bu
  947. paddd m4, m6 ; + OFFSET
  948. paddd m4, m5
  949. psrad m4, RSHIFT
  950. STORE16 [dstUq + 2*xq], 4, 1
  951. PMUL R, R, m13 ; r*rv
  952. PMUL G, G, m14 ; g*gv*g
  953. PMUL B, B, m15 ; b*bv
  954. paddd m0, m6 ; + OFFSET
  955. paddd B, G
  956. paddd m0, B
  957. psrad m0, RSHIFT
  958. STORE16 [dstVq + 2*xq], 0, 1
  959. %if cpuflag(avx2) || cpuflag(sse4)
  960. add xd, mmsize/4
  961. %else
  962. add xd, 2
  963. %endif
  964. cmp xd, wd
  965. jl %%loop_x
  966. RET
  967. %endmacro
  968. ; 1 - name
  969. ; 2 - depth
  970. ; 3 - is big endian
  971. ; 4 - is float
  972. %macro planar_rgb_to_a_fn 4
  973. cglobal planar_%1_to_a, 4, 6, 10, dst, src, w, rgb2yuv, srcA, x
  974. %if %4 && (cpuflag(sse4) || mmsize > 16)
  975. movu m7, [pb_pack_shuffle16le]
  976. %elif %3 && (cpuflag(sse4) || mmsize > 16)
  977. movu m7, [pb_shuffle16be]
  978. %endif
  979. %if %4
  980. movu m8, [pd_65535f]
  981. %endif
  982. pxor m9, m9
  983. mov srcAq, [srcq + 24]
  984. xor xq, xq
  985. %%loop_x:
  986. %if %4 ; float
  987. LOADF32 0, [srcAq + xq*4], %3, 0
  988. STORE16 [dstq + xq*2], 0, 0
  989. add xq, mmsize/4
  990. %elif %2 == 8
  991. ; only need to convert 8bit value to 16bit
  992. %if cpuflag(sse4) || mmsize > 16
  993. pmovzxbw m0, [srcAq + xq]
  994. %else
  995. movsd m0, [srcAq + xq]
  996. punpcklbw m0, m9 ; interleave bytes with zero
  997. %endif
  998. psllw m0, 6
  999. movu [dstq + xq*2], m0
  1000. add xq, mmsize/2
  1001. %else
  1002. ; only need to convert 16bit format to 16le
  1003. movu m0, [srcAq + xq*2]
  1004. %if %3 ; bigendian
  1005. %if cpuflag(sse4) || mmsize > 16
  1006. pshufb m0, m7 ; [pb_shuffle16be]
  1007. %else
  1008. psrlw m7, m0, 8
  1009. psllw m0, 8
  1010. por m0, m7
  1011. %endif
  1012. %endif
  1013. %if %2 < 16
  1014. psllw m0, (14 - %2)
  1015. %endif
  1016. movu [dstq + xq*2], m0
  1017. add xq, mmsize/2
  1018. %endif
  1019. cmp xd, wd
  1020. jl %%loop_x
  1021. RET
  1022. %endmacro
  1023. ; 1 - name
  1024. ; 2 - depth
  1025. ; 3 - is float
  1026. %macro planer_rgbxx_y_fn_decl 3
  1027. planar_rgb_to_y_fn %1le, %2, 0, %3
  1028. planar_rgb_to_y_fn %1be, %2, 1, %3
  1029. %endmacro
  1030. ; 1 - name
  1031. ; 2 - depth
  1032. ; 3 - is float
  1033. %macro planer_rgbxx_uv_fn_decl 3
  1034. planar_rgb_to_uv_fn %1le, %2, 0, %3
  1035. planar_rgb_to_uv_fn %1be, %2, 1, %3
  1036. %endmacro
  1037. ; 1 - name
  1038. ; 2 - depth
  1039. ; 3 - is float
  1040. %macro planer_rgbxx_a_fn_decl 3
  1041. planar_rgb_to_a_fn %1le, %2, 0, %3
  1042. planar_rgb_to_a_fn %1be, %2, 1, %3
  1043. %endmacro
  1044. %macro planar_rgb_y_all_fn_decl 0
  1045. planar_rgb_to_y_fn rgb, 8, 0, 0
  1046. planer_rgbxx_y_fn_decl rgb9, 9, 0
  1047. planer_rgbxx_y_fn_decl rgb10, 10, 0
  1048. planer_rgbxx_y_fn_decl rgb12, 12, 0
  1049. planer_rgbxx_y_fn_decl rgb14, 14, 0
  1050. planer_rgbxx_y_fn_decl rgb16, 16, 0
  1051. planer_rgbxx_y_fn_decl rgbf32, 32, 1
  1052. %endmacro
  1053. %macro planar_rgb_uv_all_fn_decl 0
  1054. planar_rgb_to_uv_fn rgb, 8, 0, 0
  1055. planer_rgbxx_uv_fn_decl rgb9, 9, 0
  1056. planer_rgbxx_uv_fn_decl rgb10, 10, 0
  1057. planer_rgbxx_uv_fn_decl rgb12, 12, 0
  1058. planer_rgbxx_uv_fn_decl rgb14, 14, 0
  1059. planer_rgbxx_uv_fn_decl rgb16, 16, 0
  1060. planer_rgbxx_uv_fn_decl rgbf32, 32, 1
  1061. %endmacro
  1062. %macro planar_rgb_a_all_fn_decl 0
  1063. planar_rgb_to_a_fn rgb, 8, 0, 0
  1064. planer_rgbxx_a_fn_decl rgb10, 10, 0
  1065. planer_rgbxx_a_fn_decl rgb12, 12, 0
  1066. planer_rgbxx_a_fn_decl rgb16, 16, 0
  1067. planer_rgbxx_a_fn_decl rgbf32, 32, 1
  1068. %endmacro
  1069. ; sse2 to_y only matches c speed with current implementation
  1070. ; except on floating point formats
  1071. INIT_XMM sse2
  1072. planer_rgbxx_y_fn_decl rgbf32, 32, 1
  1073. planar_rgb_uv_all_fn_decl
  1074. planar_rgb_a_all_fn_decl
  1075. ; sse4 to_a conversions are just the sse2 ones
  1076. ; except on floating point formats
  1077. INIT_XMM sse4
  1078. planar_rgb_y_all_fn_decl
  1079. planar_rgb_uv_all_fn_decl
  1080. planer_rgbxx_a_fn_decl rgbf32, 32, 1
  1081. %if HAVE_AVX2_EXTERNAL
  1082. INIT_YMM avx2
  1083. planar_rgb_y_all_fn_decl
  1084. planar_rgb_uv_all_fn_decl
  1085. planar_rgb_a_all_fn_decl
  1086. %endif
  1087. %endif ; ARCH_X86_64