variant.cpp 6.0 KB

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  1. /*
  2. Copyright (c) 2011 Arduino. All right reserved.
  3. This library is free software; you can redistribute it and/or
  4. modify it under the terms of the GNU Lesser General Public
  5. License as published by the Free Software Foundation; either
  6. version 2.1 of the License, or (at your option) any later version.
  7. This library is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  10. See the GNU Lesser General Public License for more details.
  11. You should have received a copy of the GNU Lesser General Public
  12. License along with this library; if not, write to the Free Software
  13. Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  14. */
  15. #include "pins_arduino.h"
  16. #ifdef __cplusplus
  17. extern "C" {
  18. #endif
  19. // Pin number
  20. const PinName digitalPin[] = {
  21. PA_0, //D0
  22. PA_1, //D1
  23. PA_2, //D2
  24. PA_3, //D3
  25. PA_4, //D4
  26. PA_5, //D5
  27. PA_6, //D6
  28. PA_7, //D7
  29. PA_8, //D8
  30. PA_9, //D9
  31. PA_10, //D10
  32. PA_11, //D11
  33. PA_12, //D12
  34. PA_13, //D13
  35. PA_14, //D14
  36. PA_15, //D15
  37. PB_0, //D16
  38. PB_1, //D17
  39. PB_2, //D18
  40. PB_3, //D19
  41. PB_4, //D20
  42. PB_5, //D21
  43. PB_6, //D22
  44. PB_7, //D23
  45. PB_8, //D24
  46. PB_9, //D25
  47. PB_10, //D26
  48. PB_11, //D27
  49. PB_12, //D28
  50. PB_13, //D29
  51. PB_14, //D30
  52. PB_15, //D31
  53. PC_0, //D32
  54. PC_1, //D33
  55. PC_2, //D34
  56. PC_3, //D35
  57. PC_4, //D36
  58. PC_5, //D37
  59. PC_6, //D38
  60. PC_7, //D39
  61. PC_8, //D40
  62. PC_9, //D41
  63. PC_10, //D42
  64. PC_11, //D43
  65. PC_12, //D44
  66. PC_13, //D45
  67. PC_14, //D46
  68. PC_15, //D47
  69. PD_0, //D48
  70. PD_1, //D49
  71. PD_2, //D50
  72. PD_3, //D51
  73. PD_4, //D52
  74. PD_5, //D53
  75. PD_6, //D54
  76. PD_7, //D55
  77. PD_8, //D56
  78. PD_9, //D57
  79. PD_10, //D58
  80. PD_11, //D59
  81. PD_12, //D60
  82. PD_13, //D61
  83. PD_14, //D62
  84. PD_15, //D63
  85. PE_0, //D64
  86. PE_1, //D65
  87. PE_2, //D66
  88. PE_3, //D67
  89. PE_4, //D68
  90. PE_5, //D69
  91. PE_6, //D70
  92. PE_7, //D71
  93. PE_8, //D72
  94. PE_9, //D73
  95. PE_10, //D74
  96. PE_11, //D75
  97. PE_12, //D76
  98. PE_13, //D77
  99. PE_14, //D78
  100. PE_15, //D79
  101. PF_0, //D80
  102. PF_1, //D81
  103. PF_2, //D82
  104. PF_3, //D83
  105. PF_4, //D84
  106. PF_5, //D85
  107. PF_6, //D86
  108. PF_7, //D87
  109. PF_8, //D88
  110. PF_9, //D89
  111. PF_10, //D90
  112. PF_11, //D91
  113. PF_12, //D92
  114. PF_13, //D93
  115. PF_14, //D94
  116. PF_15, //D95
  117. PG_0, //D96
  118. PG_1, //D97
  119. PG_2, //D98
  120. PG_3, //D99
  121. PG_4, //D100
  122. PG_5, //D101
  123. PG_6, //D102
  124. PG_7, //D103
  125. PG_8, //D104
  126. PG_9, //D105
  127. PG_10, //D106
  128. PG_11, //D107
  129. PG_12, //D108
  130. PG_13, //D109
  131. PG_14, //D110
  132. PG_15, //D111
  133. //Duplicated ADC Pins
  134. PA_3, //D112/A0
  135. PA_4, //D113/A1
  136. PC_0, //D114/A2
  137. PC_1, //D115/A3
  138. PC_2, //D116/A4
  139. PC_3, //D117/A5
  140. PC_4, //D118/A6
  141. PF_3, //D119/A16 - 1:FSMC_A3 2:ADC3_IN9
  142. PF_4, //D120/A17 - 1:FSMC_A4 2:ADC3_IN14
  143. PF_5, //D121/A18 - 1:FSMC_A5 2:ADC3_IN15
  144. PF_6, //D122/A19 - 1:TIM10_CH1 2:ADC3_IN4
  145. PF_7, //D123/A20 - 1:TIM11_CH1 2:ADC3_IN5
  146. PF_8, //D124/A20 - 1:TIM11_CH1 2:ADC3_IN6
  147. };
  148. #ifdef __cplusplus
  149. }
  150. #endif
  151. // ----------------------------------------------------------------------------
  152. #ifdef __cplusplus
  153. extern "C" {
  154. #endif
  155. /**
  156. * @brief System Clock Configuration
  157. * The system Clock is configured as follow :
  158. * System Clock source = PLL (HSE)
  159. * SYSCLK(Hz) = 180000000
  160. * HCLK(Hz) = 180000000
  161. * AHB Prescaler = 1
  162. * APB1 Prescaler = 4
  163. * APB2 Prescaler = 2
  164. * HSE Frequency(Hz) = 12000000
  165. * PLL_M = 6
  166. * PLL_N = 180
  167. * PLL_P = 2
  168. * PLL_Q = 7
  169. * VDD(V) = 3.3
  170. * Main regulator output voltage = Scale1 mode
  171. * Flash Latency(WS) = 5
  172. * @param None
  173. * @retval None
  174. */
  175. WEAK void SystemClock_Config(void)
  176. {
  177. RCC_ClkInitTypeDef RCC_ClkInitStruct;
  178. RCC_OscInitTypeDef RCC_OscInitStruct;
  179. RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
  180. /* Enable Power Control clock */
  181. __HAL_RCC_PWR_CLK_ENABLE();
  182. #ifdef HAL_PWR_MODULE_ENABLED
  183. /* The voltage scaling allows optimizing the power consumption when the device is
  184. clocked below the maximum system frequency, to update the voltage scaling value
  185. regarding system frequency refer to product datasheet. */
  186. __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
  187. #endif
  188. /* Enable HSE Oscillator and activate PLL with HSE as source */
  189. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  190. RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  191. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  192. RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  193. RCC_OscInitStruct.PLL.PLLM = 6;
  194. RCC_OscInitStruct.PLL.PLLN = 180;
  195. RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  196. RCC_OscInitStruct.PLL.PLLQ = 7;
  197. RCC_OscInitStruct.PLL.PLLR = 2;
  198. HAL_RCC_OscConfig(&RCC_OscInitStruct);
  199. HAL_PWREx_EnableOverDrive();
  200. /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
  201. clocks dividers */
  202. RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
  203. RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
  204. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLRCLK;
  205. RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  206. RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
  207. RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
  208. HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
  209. PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
  210. PeriphClkInitStruct.PLLSAI.PLLSAIM = 6;
  211. PeriphClkInitStruct.PLLSAI.PLLSAIN = 96;
  212. PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
  213. PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
  214. PeriphClkInitStruct.PLLSAIDivQ = 1;
  215. PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
  216. HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
  217. }
  218. #ifdef __cplusplus
  219. }
  220. #endif